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Performance from architecture: comparing a RISC and a CISC with similar hardware organization

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ASPLOS IV: Proceedings of the fourth international conference on Architectural support for programming languages and operating systems

Pages 310 - 319

https://doi.org/10.1145/106972.107003

Published: 01 April 1991 Publication History

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References

[1]

Adiletta, M.J., et al. Semiconductor Technology in a High-performance VAX System. Digital Technical Jour. hal ~, 4 (Fall 1990), pp. 43-60.

Google Scholar

[2]

Allmon, R. el al. CMOS Implementation of a 32b Compurer. 1989 ISSCC Technical Digest, Feb. 1989, pp. 80- 81.

Google Scholar

[3]

Anderson, T.E., Levy, H.M., Bershad, B.N., and Lazowska, E.D. The Interaction of Architecture and Opcrating System Design. Proc. Fourth Int. Conf. on Architectural Support for Prog. Lang. and Op. Syst., ACM/IEEE, Palo Alto, CA, April 1991, to appear.

Digital Library

Google Scholar

[4]

Clark, D.W. Pipelining and Performance in the VAX 8800. Proc. Second int. Conf. on Architectural Support for Prog. Lang. and Op. Sllst., ACM/iEEE, Palo Alto, CA, Oct. 1987, pp. 173-177.

Digital Library

Google Scholar

[5]

Clark, D.W., Bannon, P.J., and Keller, J.B. Measuri ng VAX 8800 Performance with a Histogram Hardware Monitor. Proc. 15th Annual International Symposlum on Computer Architecture, Honolulu, May 1988, pp. 176-185.

Digital Library

Google Scholar

[6]

Cocke, J. The Search for Performance in Scientific Processors. Comm. A CM 3I, 3 (March 1988), pp. 250-253.

Digital Library

Google Scholar

[7]

Cocke, J. and Markstcin, V. The evolution of RISC Technology at IBM. IBM J. of Research and Dev. 34, 1 (Jan. 1990), PP. 4-11.

Digital Library

Google Scholar

[8]

DeRosa, J., Glackemeyer, R., and Knight, T. Design and Implementation of the VAX 8600 Pipeline. Compurer 18, 5 (May 1985), pp. 38-48.

Google Scholar

[9]

DeRosa, J. and Levy, H.M. An Evaluation of Branch Architectures. Proc. 14th Annual International Symposium on Computer Architecture, Pittsburgh, PA, June 1987.

Digital Library

Google Scholar

[10]

Digital Equipment Corp. Digital Technical Journal I (Aug. 1985), DEC, Maynard, MA. This entire issue deals with the VAX 8600.

Google Scholar

[11]

Digital Equipment Corp. Digital Technical Journal 4 (Feb. 1987), DEC, Maynard, MA. This entire issue deals with the VAX 8800 family.

Google Scholar

[12]

Digital Equipment Corp. Digital Technical Journal 2, 4 (Fall 1990), DEC, Maynard, MA. This entire issue deals with the VAX 9000.

Google Scholar

[13]

Durdan, W.H. et al. An Overview of the VAX 6000 Model 400 Chip Set. Digital Technical Journal ~, 2 (Spring 1990), Digital Equipment Corp., Maynard, MA, pp. 73-83.

Google Scholar

[14]

Emer, J.S. and Clark, D.W. A Characterization of Processor Performance in the VAX-11/780. Proc. 11th Annual International Symposium on Computer Architecture, Ann Arbor, MI, June 1984, pp. 301-310.

Digital Library

Google Scholar

[15]

Fossum, T. and Fite, D. Designing a VAX for High Performance. Compcon Spring 90, IEEE, San Francisco, 1990, pp. 36-43.

Crossref

Google Scholar

[16]

Hennessy, J.L., et al., The MIPS Machine. Proc. Compcon Spring 8~, IEEE, San Francisco, 1982.

Google Scholar

[17]

International Business Machines Corp. Journal of Research and Development 34, 1 (Jan. 1990). This entire issue deals with the IBM RISC System/6000.

Google Scholar

[18]

Jouppi, N.P. and Wall, D.W. Available Instruction- Level Parallelism for Superscalar and Superpipelined Machines. Proc. Third Int. Conf. on Architectural Support for Prog. Lang. and Op. Syst., ACM/IEEE, Boston, MA, April 1989, pp. 272-282.

Digital Library

Google Scholar

[19]

Kane, G. MIPS R~O00 RISC Architecture. Englewood Cliffs, NJ: Prentice-Hall, 1987.

Google Scholar

[20]

Killian, E. MIPS cache simulation results. Personal communication, Nov. 1990.

Google Scholar

[21]

MiPS Computer Systems, Inc. MIPS Language Progmmmer's Guide, 1986.

Google Scholar

[22]

Patterson, D.A. Reduced Instruction Set Computers. Comm. ACM ~8, I (Jan. 1985), pp. 8-21.

Digital Library

Google Scholar

[23]

Patterson, D.A. and Sequin, C. RISC-i: A Reduced Instruction Set VLSI Computer. Proc. 8th Annual International Symposium on Computer Architecture, Minneapolis, May 1981, pp. 443-457.

Digital Library

Google Scholar

[24]

Pnevmatikatos, D.N. and Hill, M.D. Cache Performance of the Integer SPEC Benchmarks on a RISC. ACM Comp. Arch. News 18, 2 (June 1990), pp. 53-68.

Digital Library

Google Scholar

[25]

Radin, G. The 801 Minicomputer. Proc. Symp. on Architectural Support for Prog. Lang. and Op. Syst., ACM/IEEE, Palo Alto, CA, March 1982, pp. 39-47.

Digital Library

Google Scholar

[26]

Riordan, T., et al. Design Using the MIPS R3000/R3010 RISC Chipset. Proc. Compcon Spring 89, IEEE, San Francisco, Spring 1989.

Google Scholar

[27]

Russell, R.M. The Cray-1 Computer System. Comm. ACM 21, I (Jan. 1978), pp. 63-72.

Digital Library

Google Scholar

[28]

Saavedra-Barrera, R.H. The SPEC and Perfect Club Benchmarks: Promises and Limitations. Hot Chips Symposium I~. Santa Clara, CA, Aug. 1990.

Google Scholar

[29]

Smith, M.D., Johnson, M., and Horowitz, M.A. Limits on Multiple Instruction issue. Proc. Third Int. Conf. on Architectural Support for Prog. Lang. and Op. Syst., ACM/IEEE, Boston, MA, April 1989, pp. 290-302.

Digital Library

Google Scholar

[30]

Strecker, W.D. VAX-11/780--A Virtual Address Extension for the PDP-11 Family Computers. Proc. NCC, AFIPS Press, Montvale, N J, 1978, pp. 967-980.

Google Scholar

[31]

Systems Performance Evaluation Cooperative. SPEC Newsletter: Benchmark Results, Waterside Assoc., Fremont, CA, Fall 89, Winter 90, Spring 90.

Google Scholar

[32]

Thornton, J.E. Design of a Computer: The Control Data 6600. Glenview, IL: Scott, Foresman, and Co., 1970.

Digital Library

Google Scholar

Cited By

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Han SJiang Y(2023)RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.326810831:7(980-992)Online publication date: Jul-2023
https://doi.org/10.1109/TVLSI.2023.3268108
Yun JRustamov FKim JShin Y(2022)Fuzzing of Embedded Systems: A SurveyACM Computing Surveys10.1145/353864455:7(1-33)Online publication date: 15-Dec-2022
https://dl.acm.org/doi/10.1145/3538644
Huybrechts TMercelis SHellinckx P(2020)A Survey on the Software and Hardware-Based Influences on the Worst-Case Execution TimeAdvances on P2P, Parallel, Grid, Cloud and Internet Computing10.1007/978-3-030-61105-7_27(271-281)Online publication date: 9-Oct-2020
https://doi.org/10.1007/978-3-030-61105-7_27
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Index Terms

Performance from architecture: comparing a RISC and a CISC with similar hardware organization
1. Computer systems organization
  1. Architectures
    1. Serial architectures
2. General and reference
  1. Cross-computing tools and techniques
    1. Performance

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Information & Contributors

Information

Published In

ASPLOS IV: Proceedings of the fourth international conference on Architectural support for programming languages and operating systems

April 1991

320 pages

ISBN:0897913809

DOI:10.1145/106972

Chairman:
David A. Patterson
Univ. of California, Berkeley
,
General Chair:
Bob Rau

ACM SIGPLAN Notices Volume 26, Issue 4
Special issue of a journal and a proceedings
Apr. 1991
305 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/106973
Editor:
David A. Patterson
Univ. of California, Berkeley
Issue’s Table of Contents
ACM SIGOPS Operating Systems Review Volume 25, Issue Special Issue
Proceedings of the 4th international conference on architectural support for programming languages and operating systems
Apr. 1991
305 pages
ISSN:0163-5980
DOI:10.1145/106974
Editor:
David A. Patterson
Univ. of California, Berkeley
Issue’s Table of Contents
ACM SIGARCH Computer Architecture News Volume 19, Issue 2
Apr. 1991
305 pages
ISSN:0163-5964
DOI:10.1145/106975
Editor:
David A. Patterson
Univ. of California, Berkeley
Issue’s Table of Contents

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1991

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ASPLOS91: 4th Int'l Conference on Architecture Support for Programming Languages & Operating Systems

April 8 - 11, 1991

California, Santa Clara, USA

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Cited By

View all

Han SJiang Y(2023)RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.326810831:7(980-992)Online publication date: Jul-2023
https://doi.org/10.1109/TVLSI.2023.3268108
Yun JRustamov FKim JShin Y(2022)Fuzzing of Embedded Systems: A SurveyACM Computing Surveys10.1145/353864455:7(1-33)Online publication date: 15-Dec-2022
https://dl.acm.org/doi/10.1145/3538644
Huybrechts TMercelis SHellinckx P(2020)A Survey on the Software and Hardware-Based Influences on the Worst-Case Execution TimeAdvances on P2P, Parallel, Grid, Cloud and Internet Computing10.1007/978-3-030-61105-7_27(271-281)Online publication date: 9-Oct-2020
https://doi.org/10.1007/978-3-030-61105-7_27
Hennessy JPatterson D(2019)A new golden age for computer architectureCommunications of the ACM10.1145/328230762:2(48-60)Online publication date: 28-Jan-2019
https://dl.acm.org/doi/10.1145/3282307
Patterson D(2018)50 Years of computer architecture: From the mainframe CPU to the domain-specific tpu and the open RISC-V instruction set2018 IEEE International Solid - State Circuits Conference - (ISSCC)10.1109/ISSCC.2018.8310168(27-31)Online publication date: Feb-2018
https://doi.org/10.1109/ISSCC.2018.8310168
Uddin I(2017)One-IPC high-level simulation of microthreaded many-core architecturesInternational Journal of High Performance Computing Applications10.1177/109434201558449531:2(152-162)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1177/1094342015584495
Patterson D(2017)Reduced Instruction Set Computers Then and NowComputer10.1109/MC.2017.445120650:12(10-12)Online publication date: 1-Dec-2017
https://dl.acm.org/doi/10.1109/MC.2017.4451206
Blem EMenon JVijayaraghavan TSankaralingam K(2015)ISA WarsACM Transactions on Computer Systems10.1145/269968233:1(1-34)Online publication date: 11-Mar-2015
https://dl.acm.org/doi/10.1145/2699682
Tomar GVerma S(2009)Dynamic Multi-level Hierarchal Clustering Approach for Wireless Sensor NetworksProceedings of the UKSim 2009: 11th International Conference on Computer Modelling and Simulation10.1109/UKSIM.2009.84(563-567)Online publication date: 25-Mar-2009
https://dl.acm.org/doi/10.1109/UKSIM.2009.84
Isen CJohn LJohn E(2009)A Tale of Two ProcessorsProceedings of the 2009 SPEC Benchmark Workshop on Computer Performance Evaluation and Benchmarking10.1007/978-3-540-93799-9_4(57-76)Online publication date: 20-Jan-2009
https://dl.acm.org/doi/10.1007/978-3-540-93799-9_4
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RISC versus CISC: a tale of two chips

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