Article

Free access

Minimization of memory traffic in high-level synthesis

Authors:

David J. Kolson,

Alexandru Nicolau,

Nikil DuttAuthors Info & Claims

DAC '94: Proceedings of the 31st annual Design Automation Conference

Pages 149 - 154

https://doi.org/10.1145/196244.196316

Published: 06 June 1994 Publication History

PDF eReader

References

[1]

A. H. Aho, R. Sethi, and J. D. Ullman. Compilers: Principles, Techniques and Tools. Addison-Wesley, Reading, MA, 1986.

Digital Library

Google Scholar

[2]

V. Banerjee. Loop Transformations for Restructuring Compilers: The Foundations. Klewer Academic Publishers, Norwell, MA, 1993.

Digital Library

Google Scholar

[3]

D. Callahan, J. Cocke, and K. Kennedy. Estimating Interlock and Improving Balance for Pipelined Architectures. Proceedings of ICPP, 1987.

Google Scholar

[4]

R. Camposano. Path-Based Scheduling for Synthesis. IEEE Trans. on CAD, 10(1), 1991.

Digital Library

Google Scholar

[5]

C. Chu, M. Potkonjak, M. Thaler, and J. Rabey. HYPER: An Interactive Synthesis Environment for High Performance Real Time Applications. ICCD-89, 1989.

Crossref

Google Scholar

[6]

F. Franssen, M. van Swaaij, F. Catthoor, and H. De Man. Modeling Piece-wise Linear and Data dependent Signal Indexing for Multi-dimensional Signal Processing. 6th International Workshop on High-Level Synthesis, November 1992.

Google Scholar

[7]

D. Gajski, N. Dutt, A. Wu, and S. Lin. High Level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers. Norwell, MA., 1992.

Digital Library

Google Scholar

[8]

T. Kim and C. L. Liu. Utilization of Multiport Memories in Data Path Synthesis. 30th ACM/IEEE DAC, 1993.

Digital Library

Google Scholar

[9]

D. J. Kolson, A. Nicolau, and N. Dutt. Minimization of Memory Traffic in High-Level Synthesis. Technical Report 93-46, U.C. Irvine, October 1993.

Google Scholar

[10]

D. Kuck. The Structure of Computers and Computations, volume 1. Wiley &: Sons, 1978.

Digital Library

Google Scholar

[11]

P. E. R. Lippens, J. L. van Meerbergen, W. F. J. Verhaegh, and A. van der Werf. Allocation of Multiport Memories for Hierarchical Data Streams. ICCAD-93, 1993.

Digital Library

Google Scholar

[12]

A. Nicolau. Parallelism, Memory Anti-Aliasing and Correctness for Trace-Scheduling Compilers. PhD thesis, Yale University, March 1985.

Digital Library

Google Scholar

[13]

K. O'Brien, M. Rahmouni, and A. Jerraya. DLS: A Scheduling Algorithm for High-Level Synthesis in VHDL. EDAC-93, 1993.

Crossref

Google Scholar

[14]

C. Park, T. Kim, and C. L. Liu. Register Allocation for Data Flow Graphs with Conditional Branches and Loops. Euro- DAC '93, 1993.

Google Scholar

[15]

N. Park and A. C. Parker. Sehwa: A Software Package for Synthesis of Pipelines from Behavioral Specifications. IEEE Trans. on CAD, 7(3), 1988.

Digital Library

Google Scholar

[16]

P. Pgchmiiller, M. Glesner, and F. Longsen. High-Level Synthesis Transformations for Programmable Architectures. Euro- DAC '93, 1993.

Google Scholar

[17]

R. Potasman, J. Lis, A. Nicolau, and D. Gajski. Percolation Based Synthesis. 27th ACM/IEEE DAC, 1990.

Digital Library

Google Scholar

[18]

L. Ramachandran, D. D. Gajski, and V. Chaiyakul. An Algorithm for Array Variable Clustering. EDAC-9$, 1994.

Google Scholar

[19]

C. B. Shung et al. An Integrated CAD System for Algorithm- Specific IC Design. IEEE Trans. on CAD, April 1991.

Crossref

Google Scholar

[20]

Y. Tanaka, K. Iwasawa, Y. Umetani, and S. Gotou. Compiling techniques for first-order linear recurrences on a vector computer. Journal of Supercomputing, 4(1), March 1990.

Digital Library

Google Scholar

Cited By

View all

(2013)BibliographyMemory Allocation Problems in Embedded Systems10.1002/9781118577585.biblio(159-180)Online publication date: 4-Mar-2013
https://doi.org/10.1002/9781118577585.biblio
Wei-Kai Cheng (2006)A Transformation-Based Approach for Storage Optimization32nd Design Automation Conference10.1109/DAC.1995.250083(158-163)Online publication date: Dec-2006
https://doi.org/10.1109/DAC.1995.250083
Kolson DNicolau ADutt N(2006)Elimination of redundant memory traffic in high-level synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.54376815:11(1354-1364)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.543768
Show More Cited By

Index Terms

Minimization of memory traffic in high-level synthesis
1. Hardware
  1. Hardware test
    1. Test-pattern generation and fault simulation

Recommendations

Exploiting off-chip memory access modes in high-level synthesis
ICCAD '97: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Memory-intensive behaviors often contain large arrays that are synthesized into off-chip memories. With the increasing gap between on-chip and off-chip memory access delays, it is imperative to exploit the efficient access mode features of modern-day ...
High-Level Test Synthesis: A Survey from Synthesis Process Flow Perspective

High-level test synthesis is a special class of high-level synthesis having testability as one of the important components. This article presents a detailed survey on recent developments in high-level test synthesis from a synthesis process flow ...
Layout-driven RTL binding techniques for high-level synthesis
ISSS '96: Proceedings of the 9th international symposium on System synthesis

The importance of effective and efficient accounting of layout effects is well-established in high-level synthesis (HLS), since it allows more realistic exploration of the design space and the generation of solutions with predictable metrics. This ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

DAC '94: Proceedings of the 31st annual Design Automation Conference

June 1994

739 pages

ISBN:0897916530

DOI:10.1145/196244

Chairman:
Michael Lorenzetti
Mentor Graphics Corp., Wilsonville, OR

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 June 1994

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

DAC94

Sponsor:

EDAC
SIGDA
IEEE-CAS

DAC94: The 31st ACM/IEEE-CAS/EDAC Design Automation Conference

June 6 - 10, 1994

California, San Diego, USA

Acceptance Rates

DAC '94 Paper Acceptance Rate 100 of 260 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

14
Total Citations
View Citations
223
Total Downloads

Downloads (Last 12 months)31
Downloads (Last 6 weeks)7

Reflects downloads up to 01 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

(2013)BibliographyMemory Allocation Problems in Embedded Systems10.1002/9781118577585.biblio(159-180)Online publication date: 4-Mar-2013
https://doi.org/10.1002/9781118577585.biblio
Wei-Kai Cheng (2006)A Transformation-Based Approach for Storage Optimization32nd Design Automation Conference10.1109/DAC.1995.250083(158-163)Online publication date: Dec-2006
https://doi.org/10.1109/DAC.1995.250083
Kolson DNicolau ADutt N(2006)Elimination of redundant memory traffic in high-level synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.54376815:11(1354-1364)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.543768
Bouyssounouse BSifakis J(2005)Low power engineeringEmbedded Systems Design10.5555/2137690.2137724(450-478)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.5555/2137690.2137724
Bouyssounouse BSifakis JBouyssounouse BSifakis J(2005)Low Power EngineeringEmbedded Systems Design10.1007/978-3-540-31973-3_30(450-478)Online publication date: 2005
https://doi.org/10.1007/978-3-540-31973-3_30
Kandemir MRamanujam JChoudhary AAckland B(2002)Exploiting shared scratch pad memory space in embedded multiprocessor systemsProceedings of the 39th annual Design Automation Conference10.1145/513918.513974(219-224)Online publication date: 10-Jun-2002
https://dl.acm.org/doi/10.1145/513918.513974
Kandemir MRamanujam JIrwin JVijaykrishnan NKadayif IParikh ARabaey J(2001)Dynamic management of scratch-pad memory spaceProceedings of the 38th annual Design Automation Conference10.1145/378239.379049(690-695)Online publication date: 22-Jun-2001
https://dl.acm.org/doi/10.1145/378239.379049
Catthoor F(1999)Energy-Delay Efficient Data Storage and Transfer Architectures and MethodologiesJournal of VLSI Signal Processing Systems10.5555/331512.281322221:3(219-231)Online publication date: 1-Jul-1999
https://dl.acm.org/doi/10.5555/331512.2813222
Catthoor FDewilde PRammig FMusgrave G(1998)Energy-delay efficient data storage and transfer architecturesProceedings of the conference on Design, automation and test in Europe10.5555/368058.368343(709-715)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368343
Catthoor F(1998)Energy-delay efficient data storage and transfer architectures: circuit technology versus design methodology solutionsProceedings Design, Automation and Test in Europe10.1109/DATE.1998.655936(709-714)Online publication date: 1998
https://doi.org/10.1109/DATE.1998.655936
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Exploiting off-chip memory access modes in high-level synthesis

High-Level Test Synthesis: A Survey from Synthesis Process Flow Perspective

Layout-driven RTL binding techniques for high-level synthesis