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Path-based scheduling for synthesis

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R. CamposanoAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 10, Issue 1

Pages 85 - 93

https://doi.org/10.1109/43.62794

Published: 01 November 2006 Publication History

Abstract

A novel path-based scheduling algorithm is presented. It yields solutions with the minimum number of control steps, taking into account arbitrary constraints that limit the amount of operations in each control step. The result is a finite state machine that implements the control. Although the complexity of the algorithm is proportional to the number of paths in the control-flow graph, it is shown to be practical for large examples with thousands of nodes

Cited By

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Gu ZWan WXie JWu C(2021)Dependency Graph-based High-level Synthesis for Maximum Instruction ParallelismACM Transactions on Reconfigurable Technology and Systems10.1145/346887514:4(1-15)Online publication date: 13-Sep-2021
https://dl.acm.org/doi/10.1145/3468875
Rajmohan SNatarajan R(2019)Group influence based improved firefly algorithm for Design Space Exploration of Datapath resource allocationApplied Intelligence10.1007/s10489-018-1371-349:6(2084-2100)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1007/s10489-018-1371-3
DAB ASlama YGuan S(2018)Optimized approach based on time prediction and space chunking for polyhedron programs parallelization on multicoresProceedings of the 2nd International Conference on High Performance Compilation, Computing and Communications10.1145/3195612.3195615(22-26)Online publication date: 15-Mar-2018
https://dl.acm.org/doi/10.1145/3195612.3195615
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Path-based scheduling for synthesis
1. Theory of computation
  1. Design and analysis of algorithms
    1. Approximation algorithms analysis
    2. Online algorithms
      1. Online learning algorithms
  2. Theory and algorithms for application domains
    1. Machine learning theory
      1. Reinforcement learning

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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 10, Issue 1

November 2006

140 pages

ISSN:0278-0070

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IEEE Press

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Published: 01 November 2006

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Gu ZWan WXie JWu C(2021)Dependency Graph-based High-level Synthesis for Maximum Instruction ParallelismACM Transactions on Reconfigurable Technology and Systems10.1145/346887514:4(1-15)Online publication date: 13-Sep-2021
https://dl.acm.org/doi/10.1145/3468875
Rajmohan SNatarajan R(2019)Group influence based improved firefly algorithm for Design Space Exploration of Datapath resource allocationApplied Intelligence10.1007/s10489-018-1371-349:6(2084-2100)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1007/s10489-018-1371-3
DAB ASlama YGuan S(2018)Optimized approach based on time prediction and space chunking for polyhedron programs parallelization on multicoresProceedings of the 2nd International Conference on High Performance Compilation, Computing and Communications10.1145/3195612.3195615(22-26)Online publication date: 15-Mar-2018
https://dl.acm.org/doi/10.1145/3195612.3195615
Bandyopadhyay SBanerjee KKumar ASarkar SGerndt M(2017)PRESGenProceedings of the 2017 Workshop on Software Engineering Methods for Parallel and High Performance Applications10.1145/3085158.3086158(13-20)Online publication date: 26-Jun-2017
https://dl.acm.org/doi/10.1145/3085158.3086158
Banerjee KSarkar DMandal C(2017)Deriving bisimulation relations from path based equivalence checkersFormal Aspects of Computing10.1007/s00165-016-0406-y29:2(365-379)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1007/s00165-016-0406-y
(2016)32 & 16 Years AgoComputer10.1109/MC.2016.19049:7(4-5)Online publication date: 1-Jul-2016
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Jeong YSeo SLee J(2013)Evaluator-executor transformation for efficient pipelining of loops with conditionalsACM Transactions on Architecture and Code Optimization10.1145/2541228.255531710:4(1-23)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1145/2541228.2555317
Ben-Asher YRotem N(2013)The benefits of using variable-length pipelined operations in high-level synthesisACM Transactions on Embedded Computing Systems10.1145/2539036.253904813:3(1-23)Online publication date: 24-Dec-2013
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Li TGuo YLiu WTang MAyala JJones AMadden PCoskun A(2013)Translation validation of scheduling in high level synthesisProceedings of the 23rd ACM international conference on Great lakes symposium on VLSI10.1145/2483028.2483070(101-106)Online publication date: 2-May-2013
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Kondratyev ALavagno LMeyer MWatanabe YRosenstiel WMacii E(2012)Exploiting area/delay tradeoffs in high-level synthesisProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492963(1024-1029)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492963
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Synthesis using path-based scheduling: algorithms and exercises

A study on several combination problems of classic shop scheduling and shortest path

Global EDF-based scheduling with laxity-driven priority promotion

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