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Register allocation for software pipelined loops

Authors:

P. P. Tirumalai,

M. S. SchlanskerAuthors Info & Claims

PLDI '92: Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation

Pages 283 - 299

https://doi.org/10.1145/143095.143141

Published: 01 July 1992 Publication History

Abstract

Software pipelining is an important instruction scheduling technique for efficiently overlapping successive iterations of loops and executing them in parallel. This paper studies the task of register allocation for software pipelined loops, both with and without hardware features that are specifically aimed at supporting software pipelines. Register allocation for software pipelines presents certain novel problems leading to unconventional solutions, especially in the presence of hardware support. This paper formulates these novel problems and presents a number of alternative solution strategies. These alternatives are comprehensively tested against over one thousand loops to determine the best register allocation strategy, both with and without the hardware support for software pipelining.

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Index Terms

Register allocation for software pipelined loops
1. Software and its engineering
  1. Software notations and tools
    1. Compilers
      1. Source code generation
    2. General programming languages
      1. Language features
2. Theory of computation
  1. Semantics and reasoning
    1. Program constructs

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Published In

cover image ACM Conferences

PLDI '92: Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation

July 1992

352 pages

ISBN:0897914759

DOI:10.1145/143095

Chairman:
Stuart I. Feldman
Bell Communications Research, Morristown, NJ
,
Editor:
Richard L. Wexelblat

ACM SIGPLAN Notices Volume 27, Issue 7
July 1992
352 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/143103
Editor:
Richard Wexelblat
IDA/CDED, Alexandria, VA
Issue’s Table of Contents

Copyright © 1992 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGPLAN: ACM Special Interest Group on Programming Languages

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Association for Computing Machinery

New York, NY, United States

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Published: 01 July 1992

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PLDI92: SIGPLAN 92 Conference on Programming Language Design and Implmentation

June 15 - 19, 1992

California, San Francisco, USA

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Overall Acceptance Rate 406 of 2,067 submissions, 20%

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Lin ZMiao YXu GLi CSaarikivi OMaleki SYang F(2024)Efficient Schedule Construction for Distributed Execution of Large DNN ModelsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2024.346691335:12(2375-2391)Online publication date: Dec-2024
https://doi.org/10.1109/TPDS.2024.3466913
Lin ZMiao YXu GLi CSaarikivi OMaleki SYang F(2024)Tessel: Boosting Distributed Execution of Large DNN Models via Flexible Schedule Search2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00067(803-816)Online publication date: 2-Mar-2024
https://doi.org/10.1109/HPCA57654.2024.00067
Sutter BRaghavan PLambrechts A(2018)Coarse-Grained Reconfigurable Array ArchitecturesHandbook of Signal Processing Systems10.1007/978-3-319-91734-4_12(427-472)Online publication date: 14-Oct-2018
https://doi.org/10.1007/978-3-319-91734-4_12
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Eichenberger ADavidson EAbraham S(2014)Optimum modulo schedules for minimum register requirementsACM International Conference on Supercomputing 25th Anniversary Volume10.1145/2591635.2667171(227-236)Online publication date: 10-Jun-2014
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