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research-article

Test Synthesis with Alternative Graphs

Author:

Raimund UbarAuthors Info & Claims

IEEE Design & Test, Volume 13, Issue 1

Pages 48 - 57

https://doi.org/10.1109/54.485782

Published: 01 March 1996 Publication History

Abstract

A new, generalized approach on the basis of alternative graphs (AG) to test synthesis and analysis for digital systems is proposed. AGs permit an efficient uniform model for describing the structure, functions, as well faults in a wide class of digital circuits at different representation levels. This model also supports a wide class of test design tasks--test generation, two- or multivalued simulation, test quality analysis, statistical fault grading, testability analysis, etc. Unlike the known methods, the proposed AG approach allows the use of a single uniform model library for solving these tasks.

References

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S.M. Thatte and I.A. Abraham, "Test Generation for Microprocessors," IEEE Trans. Computers, Vol. 29, 1980, pp. 429-441.

Digital Library

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A.G. Gupta and J.R. Armstrong, "Functional Fault Modeling and Simulation for VLSI Devices," Proc. ACM/IEEE 22nd Design Automation Conf., IEEE Computer Society Press, Los Alamitos, Calif., 1985, pp. 720-726.

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D. Bhattacharya and J.P. Hayes, "A Hierarchical Test Generation Methodology for Digital Circuits," JETTA: Theory and Application, Vol. 1, 1990, pp. 103-123.

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J. Lee and J.H. Patel, "Hierarchical Test Generation Under Intensive Global Functional Constraints," Proc. 29th ACM/IEEE Design Automation Conf., IEEE CS Press, 1992, pp. 261-266.

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C.Y. Lee, "Representation of Switching Circuits by Binary Decision Diagrams," Bell System Technology J., Vol. 38, No. 7, July 1959, pp. 985-999.

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S.B. Akers, "Binary Decision Diagrams," IEEE Trans. Computers, Vol. 27, No. 6, July 1978, pp. 509-516.

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R.E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. Computers, Vol. C-35, No. 8, Aug. 1986, pp. 667-690.

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B. Becker and R. Drechsler, "How Many Decomposition Types Do We Need?" Proc. European Design and Test Conf., IEEE CS Press, 1995, pp. 438-443.

Digital Library

[10]

R. Ubar, "Test Generation for Digital Circuits Using Alternative Graphs," (in Russian), Proc. Tallinn Technical Univ., No. 409, Tallinn Technical Univ., Tallinn, Estonia, 1976, pp. 75-81.

[11]

R. Ubar, "Test Pattern Generation for Digital Systems on the Vector AG-Model," Proc. 13th Int'l Symp. Fault-Tolerant Computing, IEEE CS Press, 1983, pp. 347-351.

[12]

R. Ubar, "Alternative Graphs and Technical Diagnosis of Digital Devices," (in Russian), Electronic Technique, Vol. 8, No. 5, May 1988, pp. 33-57.

[13]

Fehler in automaten, {Faults in Automata}, D. Bochmann and R. Ubar, eds., VEB Verlag Technik, Berlin, 1989.

[14]

F. Corno, et al., "Improving Topological ATPG with Symbolic Techniques," Proc. IEEE VLSI Test Symp., IEEE CS Press, 1995, pp. 338-343.

Digital Library

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R. Ubar, "Fault Diagnosis in VLSI Devices," Proc. Estonian Acad. of Sciences, Engineering, No. 1, Estonian Acad. of Sciences, Tallinn, Estonia, 1995, pp. 51-67.

[16]

R. Ubar, et al., "A PC-Based CAD System for Training Digital Test," Proc. Fifth Eurochip Workshop on VLSI Design Training, CMP/Eurochip, Grenoble, 1994, pp. 152-157.

Cited By

Gorev MUbar RDevadze SNebel WAtienza D(2015)Fault simulation with parallel exact critical path tracing in multiple core environmentProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757085(1180-1185)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2757085
Zolotorevich LIl'Inkova A(2010)Development of tests for VLSI circuit testability at the upper design levelsAutomation and Remote Control10.1134/S000511791009011071:9(1888-1898)Online publication date: 1-Sep-2010
https://dl.acm.org/doi/10.1134/S0005117910090110
Ubar RRaik JEvartson TKruus MLensen H(2006)Diagnostic modelling of digital systems with multi-level decision diagramsProceedings of the 17th IASTED international conference on Modelling and simulation10.5555/1167113.1167151(207-212)Online publication date: 24-May-2006
https://dl.acm.org/doi/10.5555/1167113.1167151
Show More Cited By

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Published In

cover image IEEE Design & Test

IEEE Design & Test Volume 13, Issue 1

March 1996

84 pages

ISSN:0740-7475

Issue’s Table of Contents

Copyright © Copyright © 1996 IEEE. All Rights Reserved.

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 March 1996

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Cited By

Gorev MUbar RDevadze SNebel WAtienza D(2015)Fault simulation with parallel exact critical path tracing in multiple core environmentProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757085(1180-1185)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2757085
Zolotorevich LIl'Inkova A(2010)Development of tests for VLSI circuit testability at the upper design levelsAutomation and Remote Control10.1134/S000511791009011071:9(1888-1898)Online publication date: 1-Sep-2010
https://dl.acm.org/doi/10.1134/S0005117910090110
Ubar RRaik JEvartson TKruus MLensen H(2006)Diagnostic modelling of digital systems with multi-level decision diagramsProceedings of the 17th IASTED international conference on Modelling and simulation10.5555/1167113.1167151(207-212)Online publication date: 24-May-2006
https://dl.acm.org/doi/10.5555/1167113.1167151
Raik JNõmmeots TUbar R(2005)A New Testability Calculation Method to Guide RTL Test GenerationJournal of Electronic Testing: Theory and Applications10.1007/s10836-005-5288-521:1(71-82)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.1007/s10836-005-5288-5
Li TGuo YLi SZhu D(2005)Applying constraint logic programming to predicate abstraction of RTL verilog descriptionsProceedings of the 4th Mexican international conference on Advances in Artificial Intelligence10.1007/11579427_18(175-184)Online publication date: 14-Nov-2005
https://dl.acm.org/doi/10.1007/11579427_18
Li TGuo YLi SLiu G(2005)Predicate abstraction of RTL verilog descriptions using constraint logic programmingProceedings of the Third international conference on Automated Technology for Verification and Analysis10.1007/11562948_15(174-186)Online publication date: 4-Oct-2005
https://dl.acm.org/doi/10.1007/11562948_15
Raik JUbar RDevadze SJutman A(2005)Efficient single-pattern fault simulation on structurally synthesized BDDsProceedings of the 5th European conference on Dependable Computing10.1007/11408901_25(332-344)Online publication date: 20-Apr-2005
https://dl.acm.org/doi/10.1007/11408901_25
Li TGuo YLi SGarrett DLach JZukowski C(2004)Assertion-based automated functional vectors generation using constraint logic programmingProceedings of the 14th ACM Great Lakes symposium on VLSI10.1145/988952.989021(288-291)Online publication date: 26-Apr-2004
https://dl.acm.org/doi/10.1145/988952.989021
Ubar RJutman APeng Z(2001)Timing simulation of digital circuits with binary decision diagramsProceedings of the conference on Design, automation and test in Europe10.5555/367072.367324(460-466)Online publication date: 13-Mar-2001
https://dl.acm.org/doi/10.5555/367072.367324
Ubar RRaik J(2000)Efficient Hierarchical Approach to Test Generation for Digital SystemsProceedings of the 1st International Symposium on Quality of Electronic Design10.5555/850998.855860Online publication date: 20-Mar-2000
https://dl.acm.org/doi/10.5555/850998.855860
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