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research-article

The dynamic reduction of fault simulation

Published: 01 November 2006 Publication History

Abstract

Efficient strategies to perform selectively fault-free simulation, critical path tracing in fanout-free regions, and fault simulation of stem faults in a parallel pattern evaluation environment are presented and analyzed in an implementation-independent manner. The dynamic changes in the complexity of the fault simulation components as the fault simulation progresses and faults are detected are shown to be extremely significant. In particular, fault-free simulation tends quickly to become more expensive than both the critical path tracing within fanout-free regions and the explicit simulation of stem faults. In addition, the presence of redundant faults is shown to have an inhibiting effect on the reduction of the fault simulation complexity

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  • (2010)Efficient fault simulation on many-core processorsProceedings of the 47th Design Automation Conference10.1145/1837274.1837369(380-385)Online publication date: 13-Jun-2010
  1. The dynamic reduction of fault simulation

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      cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
      IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 12, Issue 1
      November 2006
      186 pages

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      IEEE Press

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      Published: 01 November 2006

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      • (2010)Efficient fault simulation on many-core processorsProceedings of the 47th Design Automation Conference10.1145/1837274.1837369(380-385)Online publication date: 13-Jun-2010

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