research-article

The Full-Use-of-Suitable-Spares (FUSS) Approach to Hardware Reconfiguration for Fault-Tolerant Processor Arrays

Authors:

M. Chean,

J. A. B. FortesAuthors Info & Claims

IEEE Transactions on Computers, Volume 39, Issue 4

Pages 564 - 571

https://doi.org/10.1109/12.54851

Published: 01 April 1990 Publication History

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Abstract

A general approach to hardware recognition is proposed for VLSI/WSI fault-tolerant processor arrays. The technique, called full use of suitable spares (FUSS), uses an indicator vector, the surplus vector, to guide the replacement of faulty processors within an array. Analytical study of the general FUSS algorithm shows that there is a linear relationship between the array size and the area of interconnect required for reconfiguration to be 100% successful. In an instance of FUSS, called simple FUSS, reconfiguration is done by shifting up to or down the surplus vector's entries. The surplus vector is progressively updated after each column is reconfigured. The reconfiguration is successful when the surplus vector becomes null. Simple FUSS is discussed in detail and evaluated. Simulations show that when the number of faulty processors is equal to that of space processors, simple FUSS can achieve a probability of survival as high as 99%.

References

[1]

{1} M. Chean and J. A. B. Fortes, "A taxonomy for reconfiguration techniques for fault-tolerant processor arrays," IEEE Computer Mag., Jan. 1989.

Crossref

Google Scholar

[2]

{2} R. Negrini and R. Stefanelli, "Comparative evaluation of space- and time-redundancy approaches for WSI processing arrays," in Wafer Scale Integration, G. Saucier and J. Trilhe, Eds., New York: Elsevier Science, 1986, pp. 207-222.

Google Scholar

[3]

{3} L. Jervis, F. Lombardi, and D. Sciuto, "Orthogonal mapping: A reconfiguration strategy for fault tolerant VLSI/WSI 2-D arrays," in Proc. Int. Workshop. Defect Tolerance VLSI Syst., Oct. 1988.

Google Scholar

[4]

{4} F. Lombardi, D. Sciuto, and R. Stefanelli, "A technique for reconfiguring two dimensional VLSI arrays," in Proc. Real-Time Syst. Symp., 1987, pp. 44-53.

Google Scholar

[5]

{5} F. Lombardi, R. Negrini, and R. Stefanelli, "Reconfiguration of VLSI arrays: A covering approach," in Proc. 17th Int. Symp. Fault-Tolerant Comput. Syst., 1987, pp. 251-256.

Google Scholar

[6]

{6} M. G. Sami and R. Stefanelli, "Fault-tolerance and functional reconfiguration in VLSI arrays," in Proc. Int. Symp. Circuits Syst., 1986, pp. 643-648.

Google Scholar

[7]

{7} M. Chean, "Hardware reconfiguration for fault-tolerant processor arrays," Ph.D. dissertation, School of Elec. Eng., Purdue Univ., 1989.

Google Scholar

[8]

{8} L. Snyder, "Introduction to the configurable highly parallel computers," IEEE Comput. Mag., vol. 15, pp. 47-55, Jan 1982.

Digital Library

Google Scholar

[9]

{9} N. Lopez-Benitez and J. A. B. Fortes, "Detailed modeling of fault-tolerant processor arrays," in Proc. 19th Int. Symp. Fault-Tolerant Comput. Syst., June 1989, pp. 545-552.

Google Scholar

[10]

{10} M. G. Sami and R. Stefanelli, "Reconfigurable architectures for VLSI processing arrays," Proc. IEEE, vol. 74, pp. 712-722, May 1986.

Crossref

Google Scholar

[11]

{11} H. Y. Youn and A. D. Singh, "Efficient reconfiguration of WSI arrays with bounded channel width," in Proc. Int. Workshop. Hardware Fault Tolerance Multiprocessors, June 1989, pp. 24-26.

Google Scholar

[12]

{12} M. Chean and J. A. B. Fortes, "FUSS: A reconfiguration scheme for fault-tolerant processor arrays," in Proc. Int. Workshop. Hardware Fault Tolerance Multiprocessors, June 1989, pp. 30-32.

Google Scholar

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The Full-Use-of-Suitable-Spares (FUSS) Approach to Hardware Reconfiguration for Fault-Tolerant Processor Arrays

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cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 39, Issue 4

April 1990

188 pages

ISSN:0018-9340

Editor:
Ming T. Liu
Ohio State Univ., Columbus

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IEEE Computer Society

United States

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Published: 01 April 1990

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Lee CKim HPark HKim SOh HHa SGivargis TDonlin A(2010)A task remapping technique for reliable multi-core embedded systemsProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/1878961.1879014(307-316)Online publication date: 24-Oct-2010
https://dl.acm.org/doi/10.1145/1878961.1879014
Yang COrailoglu AHa SChoi KDutt NTeich J(2007)Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedulesProceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1289816.1289824(15-20)Online publication date: 30-Sep-2007
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Mahapatra NDutt S(2001)Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected ArraysJournal of Parallel and Distributed Computing10.1006/jpdc.2001.170261:10(1391-1411)Online publication date: 1-Oct-2001
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Horita TTakanami I(2000)Fault-Tolerant Processor Arrays Based on the 1$\frac{1}{2}$-Track Switches with Flexible Spare DistributionsIEEE Transactions on Computers10.1109/12.86221449:6(542-552)Online publication date: 1-Jun-2000
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John LJohn E(1998)A dynamically reconfigurable interconnect for array processorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/92.6612576:1(150-157)Online publication date: 1-Mar-1998
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Hamilton SOrailoglu A(1998)Efficient Self-Recovering ASIC DesignIEEE Design & Test10.1109/54.73592415:4(25-35)Online publication date: 1-Oct-1998
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Das CMohapatra P(1995)On Dependability Evaluation of Mesh-Connected ProcessorsIEEE Transactions on Computers10.1109/12.46438644:9(1073-1084)Online publication date: 1-Sep-1995
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Mazzaferri RMurray T(1995)The Connection Network Class for Fault Tolerant MeshesIEEE Transactions on Computers10.1109/12.36800244:1(131-138)Online publication date: 1-Jan-1995
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Ramirez JMelhem R(1994)Computational Arrays with Flexible RedundancyIEEE Transactions on Computers10.1109/12.27848043:4(413-430)Online publication date: 1-Apr-1994
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Abstract

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Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays

On integrating fault-tolerant reconfiguration and functional reconfiguration in highly defective VLSI and WSI processor arrays

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