An error recoverable structure based on complementary logic and alternating-retry
Pages 885 - 894
Abstract
Modern VLSI circuits provide adequate on-chip resources. So that online testing and retry integrated into a chip are absolutely necessary for system-on-a-chip technology. This paper firstly proposes a general online testing plus retrying structure. Obviously, although retry can mask transient or intermittent faults, it is useless for handling permanent faults generally. To solve this problem, this paper presents a novel dual modular redundancy (DMR) structure using complementary logic--alternating-complementary logic (CL-ACL) switching mode. During error-free operation, the CL-ACL structure operates by complementary logic mode. After an error is detected, it retries by alternating logic mode. If all errors belong to single or multiple temporary 0/1-error or stuck-at-error produced by one module, then these errors can be corrected effectively. The results obtained from the simulation validate the correctness of the CL-ACL structure. Analytic results show that the delay of the CL-ACL structure is dramatically less than that of a DMR structure using alternating-complementary logic mode.
References
[1]
{1} Gwennap L. Estimating IC manufacturing costs. Microprocessor Report, Aug., 1993, p.15.
[2]
{2} Castillo X, McConnel S R, Siewiorek D P. Derivation and calibration of a transient error reliability model. IEEE Trans. Computers, 1982, 31(7): 658-671.
[3]
{3} Iyer I, Rossetti D. A measurement-based model for workload dependence of CPU errors. IEEE Trans. Computers, 1986, 35(6): 511-519.
[4]
{4} Karri R, Nicolaidis M. Online VLSI testing. IEEE Design & Test of Computers, 1998, 15(4): 12-16.
[5]
{5} Nicolaidis M. On-line testing for VLSI: State of the art and trends. Integration, the VLSI Journal, 1998, 26(1-2): 197-209.
[6]
{6} Electronic Design Automation Industry Council. EDA roadmap taskforce report -- Design of microprocessors. Austin: Silicon Integration Initiative, Inc., 1999.
[7]
{7} Lala P K. Fault-Tolerant and Fault-Testable Hardware Design. N J: Prentice-Hall, 1985.
[8]
{8} Johnson B W. Design and Analysis of Fault Tolerant Digital Systems. Addison-Wesley, 1989.
[9]
{9} Giacelli M L. Fault handling on the IBM 4341 processor. In Proc. 11th Int. Symp. Fault-Tolerant Computing, Portland, Maine, 1981, pp.9-12.
[10]
{10} Webb C F, Liptay J S. A high-frequency custom CMOS S/390 microprocessors. IBM J. Research and Development, 1997, 41(4/5): 463-474.
[11]
{11} Spainhower L, Gregg T A. G4: A fault-tolerant CMOS mainframe. In Proc. 28th Int. Symp. Fault-Tolerant Computing, Munich, 1998, pp.432-440.
[12]
{12} Pradhan D K. Fault-Tolerant Computer System Design. N J: Prentice-Hall, 1996.
[13]
{13} Li C-C J, Chen S-K, Fuchs W K, Hwu W-M W. Compiler-based multiple instruction retry. IEEE Trans. Computers, 1995, 44(1): 35-46.
[14]
{14} Alewine N J, Chen S-K, Fuchs W K, Hwu'W-M W. Compiler assisted multiple instruction rollback recovery using a read buffer. IEEE Trans. Computers, 1995, 44(9): 1096-1107.
[15]
{15} Chen S-K, Fuchs W K. Compiler-assisted multiple instruction word retry for VLIW architecture. IEEE Trans. Parallel and Distributed Systems, 2001, 12(12): 1293-1304.
[16]
{16} Bruckert W F, Josephson R E. Designing reliability into the VAX 8600 systems. Digital Technical Journal of Digital Equipment Corporation, 1985, 1(1): 71-77.
[17]
{17} Tamir Y, Tremblay M. High-performance fault-tolerant VLSI systems using micro rollback. IEEE Trans. Computers, 1990, 39(4): 548-554.
[18]
{18} Orailoǧlu A, Karri R. Automatic synthesis of self-recovering VLSI systems. IEEE Trans. Computers, 1996, 45(2): 131-142.
[19]
{19} Chean M, Fortes J A B. The full-use-of-suitable-spares (FUSS) approach to hardware reconfiguration for fault-tolerant processor arrays. IEEE Trans. Computers, 1990, 39(4): 564-571.
[20]
{20} Jiang J H. Alternating-complementary locator and its use for error location in dual-modular redundancy with comparison structure. Journal of Computer Research and Development, 2001, 38(6): 754-764. (in Chinese)
[21]
{21} Lo J C. Online current testing. IEEE Design and Test of Computers, 1998, 15(4): 49-56.
[22]
{22} Lo J C, Daly J C, Nicolaidis M. A strongly code disjoint built-in current sensor for strongly fault secure static CMOS realizations. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 1995, 14(11): 1402-1407.
[23]
{23} Guerra L M, Potkonjak M, Rabaey J M. Behavior-level synthesis of heterogeneous BISR recoverable ASICs. IEEE Trans. VLSI Systems, 1998, 6(1): 58-66.
[24]
{24} Kim K, Karri R, Potkonjak M. Configurable space processors: A new approach to system-level fault tolerance. In Proc. Int. Workshop Defect and Fault Tolerance in VLSI Systems, Piscataway, 1996, pp.295-303.
[25]
{25} Orailoǧlu A. Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs for multiple faults. In Proc. Int. Conf. Computer Design, Los Alamitos: IEEE Computer Society, 1996, pp.112-117.
[26]
{26} Hamilton S N, Orailoǧlu A. Efficient self-recovering ASIC design. IEEE Design and Test of Computers, 1998, Fall, pp.25-35.
[27]
{27} Jiang J H, Min Y H, Peng C L. Fault-tolerant systems with concurrent error locating capability. Journal of Computer Science and Technology, 2003, 18(2): 190-200.
Index Terms
- An error recoverable structure based on complementary logic and alternating-retry
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Published: 01 November 2005
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