[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
research-article

Selection of a fault model for fault diagnosis based on unique responses

Published: 01 November 2010 Publication History

Abstract

In this paper, we describe a preprocessing step to fault diagnosis of an observed response obtained from a faulty chip. In this step, a fault model for diagnosing the observed response is selected. This step allows fault diagnosis to be performed based on a single fault model after identifying the most appropriate one. We describe a specific implementation of this preprocessing step based on what is referred to as the unique output response of a fault model. As an example, we apply it to the diagnosis of multiple stuck-at faults, selecting between single and double stuck-at faults as the fault model for diagnosis. Experimental results demonstrate improvements compared to diagnosis based on single stuck-at faults, and compared to diagnosis based on both single and double stuck-at faults. We also discuss the use of a subset of double stuck-at faults for diagnosis, and the application of the proposed preprocessing step with other fault models.

References

[1]
M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design. Piscataway, NJ: IEEE Press, 1995.
[2]
J. A. Waicukauski and E. Lindbloom, "Failure diagnosis of structured VLSI," IEEE Des. Test Comput., vol. 6, no. 4, pp. 49-60, Aug. 1989.
[3]
T. Bartenstein, D. Heaberlin, L. Huisman, and D. Sliwinski, "Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm," in Proc. Int. Test Conf., Oct. 2001, pp. 287-296.
[4]
M. Abramovici and M. A. Breuer, "Multiple fault diagnosis in combinational circuits based on an effect-cause analysis," IEEE Trans. Comput., vol. 29, no. 6, pp. 451-460, Jun. 1980.
[5]
H. Cox and J. Rajski, "A method of fault analysis for test generation and fault diagnosis," IEEE Trans. Comput.-Aided Des. Integr. Circuit Syst., vol. 7, no. 7, pp. 813-833, Jul. 1988.
[6]
N. Yanagida, H. Takahashi, and Y. Takamatsu, "Efficiency improvements for multiple fault diagnosis of combinational circuits," in Proc. Asian Test Symp., Nov. 1994, pp. 82-87.
[7]
Z. Wang, M. Marek-Sadowska, K.-H. Tsai, and J. Rajski, "Multiple fault diagnosis using n-detection tests," in Proc. Int. Conf. Comput. Des., Oct. 2003, pp. 198-201.
[8]
S. D. Millman, E. J. McCluskey, and J. M. Acken, "Diagnosing CMOS bridging faults with stuck-at fault dictionaries," in Proc. Int. Test Conf., 1990, pp. 860-870.
[9]
S. Chakravarty and Y. Gong, "An algorithm for diagnosing two-line bridging faults in combinational circuits," in Proc. Des. Autom. Conf., Jun. 1993, pp. 520-524.
[10]
B. Chess, D. B. Lavo, F. J. Ferguson, and T. Larrabee, "Diagnosis of realistic bridging faults with single stuck-at information," in Proc. Int. Conf. Comput.-Aided Des., Nov. 1995, pp. 185-192.
[11]
R. C. Aitken and P. C. Maxwell, "Better models or better algorithms? Techniques to improve fault diagnosis," HP J., pp. 110-116, Feb. 1995.
[12]
R. C. Aitken, "A comparison of defect models for fault location with Iddq measurements," in Proc. Int. Test Conf., Sep. 1992, pp. 778-787.
[13]
S. Chakravarty and M. Liu, "Algorithms for current monitor based diagnosis of bridging and leakage faults," in Proc. Des. Autom. Conf., 1992, pp. 353-356.
[14]
J. Saxena, K. M. Butler, H. Balachandran, D. B. Lavo, B. Chess, T. Larrabee, and F. J. Ferguson, "On applying non-classical defect models to automated diagnosis," in Proc. Int. Test Conf., Oct. 1998, pp. 748-757.
[15]
S. Venkataraman and S. B. Drummonds, "A technique for logic fault diagnosis of interconnect open defects," in Proc. VLSI Test Symp., Apr. 2000, pp. 313-318.
[16]
J. D. Lesser and J. J. Shedletsky, "An experimental delay test generator for LSI logic," IEEE Trans. Comput., vol. C-29, no. 3, pp. 235-248, Mar. 1980.
[17]
P. Girard, C. Landrault, and S. Pravossoudovitch, "A novel approach to delay-fault diagnosis," in Proc. Des. Autom. Conf., 1992, pp. 357-360.
[18]
M. Sivaraman and A. J. Strojwas, "A diagnosability metric for parametric path delay faults," in Proc. VLSI Test Symp., Apr. 1996, pp. 316-322.
[19]
Y.-C. Hsu and S. K. Gupta, "A new path-oriented effect-cause methodology to diagnose delay failures," in Proc. Int. Test Conf., 1998, pp. 758-767.
[20]
J. Richman and K. R. Bowden, "The modern fault dictionary," in Proc. Int. Test Conf., 1985, pp. 696-702.
[21]
P. G. Ryan, S. Rawat, and W. K. Fuchs, "Two-stage fault location," in Proc. Int. Test Conf., 1991, pp. 963-968.
[22]
D. B. Lavo, B. Chess, T. Larrabee, and I. Hartanto, "Probabilistic mixed-model fault diagnosis," in Proc. Int. Test Conf., Oct. 1998, pp. 1084-1093.
[23]
R. D. Blanton, J. T. Chen, R. Desineni, K. N. Dwarakanath, W. Maly, and T. J. Vogels, "Fault tuples in diagnosis of deep-submicron circuits," in Proc. Int. Test Conf., 2002, pp. 233-241.
[24]
S. Venkataraman and S. B. Drummonds, "POIROT: A logic fault diagnosis tool and its applications," in Proc. Int. Test Conf., 2000, pp. 253-262.
[25]
S. Holst and H.-J.Wunderlich, "Adaptive debug and diagnosis without fault dictionaries," in Proc. Eur. Test Symp., 2007, pp. 7-12.
[26]
I. Pomeranz and S. M. Reddy, "Selection of a fault model for fault diagnosis based on unique responses," in Proc. Des. Autom. Test Eur. Conf., 2009, pp. 994-999.
[27]
D. B. Lavo and T. Larrabee, "Making cause-effect cost effective: Low-resolution fault dictionaries," in Proc. Int. Test Conf., Oct. 2001, pp. 278-286.
[28]
P. Bernardi, M. Grosso, M. Rebaudengo, and M. S. Reorda, "A pattern ordering algorithm for reducing the size of fault dictionaries," in Proc. VLSI Test Symp., Apr. 2006, pp. 386-391.
[29]
W. Zou, W.-T. Cheng, S. M. Reddy, and H. Tang, "Speeding up effectcause defect diagnosis using a small dictionary," in Proc. VLSI Test Symp., 2007, pp. 225-230, Paper 6B-2.
[30]
S. Sengupta, S. Kundu, S. Chakravarty, P. Parvathala, R. Galivanche, G. Kosonocky, M. Rodgers, and T. M. Mak, "Defect-based tests: A key enabler for successful migration to structural test," Intel Technol. J., Q.1, pp. 1-12, 1999.
[31]
V. Krishnaswamy, A. B. Ma, and P. Vishakantaiah, "A study of bridging defect probabilities on a pentium (TM) 4 CPU," in Proc. Int. Test Conf., 2001, pp. 688-695.
[32]
J. Waicukauski, E. Lindbloom, B. Rosen, and V. Iyengar, "Transition fault simulation," IEEE Design Test, vol. 4, no. 2, pp. 32-38, Apr. 1987.
  1. Selection of a fault model for fault diagnosis based on unique responses

      Recommendations

      Comments

      Please enable JavaScript to view thecomments powered by Disqus.

      Information & Contributors

      Information

      Published In

      cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems
      IEEE Transactions on Very Large Scale Integration (VLSI) Systems  Volume 18, Issue 11
      November 2010
      120 pages

      Publisher

      IEEE Educational Activities Department

      United States

      Publication History

      Published: 01 November 2010
      Received: 08 December 2008
      Revised: 10 March 2008

      Author Tags

      1. Bridging faults
      2. bridging faults
      3. fault diagnosis
      4. multiple stuck-at faults
      5. single stuck-at faults
      6. transition faults

      Qualifiers

      • Research-article

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • 0
        Total Citations
      • 0
        Total Downloads
      • Downloads (Last 12 months)0
      • Downloads (Last 6 weeks)0
      Reflects downloads up to 26 Dec 2024

      Other Metrics

      Citations

      View Options

      View options

      Media

      Figures

      Other

      Tables

      Share

      Share

      Share this Publication link

      Share on social media