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research-article

Graphical I_DDQ signatures reduce defect level and yield loss

Authors:

Michael L. Bushnell,

Vishwani D. AgrawalAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 15, Issue 11

Pages 1245 - 1255

https://doi.org/10.1109/TVLSI.2007.904128

Published: 01 November 2007 Publication History

Abstract

We propose a new I_DDQ testing signature, the graphical I_DDQ signature. We discovered that noise, in the entire set of current measurements for a chip, is a vastly superior feature for classifying chips as good or bad, compared to present methods. The measured I_DDQ current as a function of vectors is defined here as the signature. We examine the shape of the waveform defined by the total set of the I_DDQ measurements, to extract the number of bands that all of the current measurements cluster into, the width and separation of the bands and current glitches or noise among all I_DDQ measurements. We examined the I_DDQ signatures of all SEMATECH experiment chips that were classified as good or bad by a combination of functional, delay, and scan voltage tests. A single I_DDQ threshold, whether absolute or differential, cannot separate good/bad chips reliably. Good chip signatures contain discrete levels (or bands) of varying widths and separations. A faulty chip almost always displays noise and glitches in the band structure. The graphical I_DDQ classifier shows very high accuracy for SEMATECH test data with a test escape rate of 5.97%, compared with 7.5% for the single threshold method, 7.6% for current differences and 7.5% for the Δ I_DDQ method. The graphical I_DDQ method had a 1.2% test overkill, compared with 2.3% for the single threshold method, 6.1% for current differences and 7.0% for Δ I_DDQ.

References

[1]

{1} S. Chakravarty and P. Thadikaran, Introduction to I _DDQ Testing. Boston, MA: Springer, 1997.

Digital Library

[2]

{2} T. Williams, R. Dennard, R. Kapur, M. Mercer, and W. Maly, "I _DDQ test: Sensitivity analysis of scaling," in Proc. Int. Test Conf., 1996, pp. 786-792.

Digital Library

[3]

{3} A. Gattiker and W. Maly, "Current signatures," in Proc. VLSI Test Symp., 1996, pp. 112-117.

Digital Library

[4]

{4} T. Henry and T. Soo, "Burn-in elimination of a high volume microprocessor using I _DDQ," in Proc. Int. Test Conf., 1996, pp. 242-249.

Digital Library

[5]

{5} J. Li and E. McCluskey, "I _DDQ data analysis using current signature," in Proc. Int. Workshop I _DDQ Testing, 1998, pp. 12-14.

Digital Library

[6]

{6} P. Maxwell, P. O'Neill, R. Aitken, R. Dudley, N. Jaarsma, M. Quach, and D. Wiseman, "Current ratios: A self-scaling technique for production I _DDQ testing," in Proc. Int. Test Conf., 1999, pp. 738-746.

Digital Library

[7]

{7} C. Thibeault, "A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures," in Proc. VLSI Test Symp., 1997, pp. 80-85.

Digital Library

[8]

{8} M. Sachdev, "Current-based testing for deep-submicron VLSIs," IEEE Design Test Comput., vol. 18, no. 2, pp. 76-84, Mar./Apr. 2001.

Digital Library

[9]

{9} P. Nigh, W. Needham, K. Butler, P. Maxwell, and R. Aitken, "An experimental study comparing the relative effectiveness of functional, scan I _DDQ, and delay-fault testing," in Proc. VLSI Test Symp., Apr./May 1997, pp. 459-464.

Digital Library

[10]

{10} M. Levi, "CMOS is most testable," in Proc. Int. Test Conf., 1981, pp. 217-220.

[11]

{11} Y. Malaiya and S. Su, "A new fault model and testing technique for CMOS devices," in Proc. Int. Test Conf., 1982, pp. 25-34.

[12]

{12} J. Acken, "Testing for bridging faults (shorts) in CMOS circuits," in Proc. Des. Autom. Conf., 1983, pp. 717-718.

Digital Library

[13]

{13} W. Needham, C. Prunty, and E. Yeoh, "High volume microprocessor test escapes, an analysis of defects our tests are missing," in Proc. Int. Test Conf., 1998, pp. 25-34.

Digital Library

[14]

{14} R. K. Gulati and C. F. Hawkins, I _DDQ Testing of VLSI Circuits. Boston, MA: Springer, 1993.

[15]

{15} Y. K. Malaiya and R. Rajsuman, Bridging Faults and I _DDQ Testing. Los Alamitos, California: IEEE Computer Society, 1992.

[16]

{16} R. Rajsuman, I _DDQ Testing for CMOS VLSI. Boston, MA: Artech House, 1995.

[17]

{17} M. Sachdev, Defect Oriented Testing for CMOS Analog and Digital Circuits. Boston, MA: Springer, 1998.

Digital Library

[18]

{18} W. Jiang and B. Vinnakota, "IC test using the energy consumption ratio," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 19, no. 1, pp. 129-141, Jan. 2000.

Digital Library

[19]

{19} S. Kim, S. Chakravarty, and B. Vinnakota, "Analysis of the delay defect detection capability of the ECR test method," in Proc. Int. Test Conf., 2000, pp. 1060-1069.

Digital Library

[20]

{20} B. Vinnakota, "Deep submicron defect detection with the energy consumption ratio," in Proc. Int. Conf. Comput.-Aided Des., 1999, pp. 467-470.

Digital Library

[21]

{21} A. Gattiker and W. Maly, "Current signatures: Application," in Proc. Int. Test Conf., 1998, pp. 1168-1177.

Digital Library

[22]

{22} C. Thibeault, "On the comparison of delta I _DDQ and I _DDQ testing," in Proc. VLSI Test Symp., 1999, pp. 143-150.

Digital Library

[23]

{23} A. Miller, "I _DDQ testing in deep submicron integrated circuits," in Proc. Int. Test Conf., 1999, pp. 724-729.

Digital Library

[24]

{24} B. Kruseman, R. van Veen, and K. van Kaam, "The future of delta I _DDQ testing," in Proc. Int. Test Conf., 2001, pp. 101-110.

Digital Library

[25]

{25} S. Jandhyala, H. Balachandran, and A. Jayasumana, "Clustering based techniques for I _DDQ testing," in Proc. Int. Test Conf., 1999, pp. 730-737.

Digital Library

[26]

{26} S. Jandhyala, H. Balachandran, M. Sengupta, and A. Jayasumana, "Clustering based evaluation of I _DDQ measurements: Applications in testing and classification of ICs," in Proc. VLSI Test Symp., 2000, pp. 444-449.

Digital Library

[27]

{27} Y. Okuda, "DECOUPLE: Defect current detection in deep submicron I _DDQ," in Proc. Int. Test Conf., 2000, pp. 199-206.

Digital Library

[28]

{28} P. Variyam, "Increasing the I _DDQ test resolution using current prediction," in Proc. Int. Test Conf., 2000, pp. 217-224.

Digital Library

[29]

{29} C. Thibeault, "Detection and location of faults and defects using digital signal processing," in Proc. VLSI Test Symp., 1995, pp. 262-267.

Digital Library

[30]

{30} B. Chess, "Method of improving the quality and efficiency of I _DDQ testing," U.S. Patent 5914615, Jun. 22, 1999.

[31]

{31} Y. Okuda, "Method and apparatus of testing and analyzing CMOS integrated circuit," U.S. Patent 6515500, Feb. 4, 2003.

[32]

{32} C. Lu, C. Lee, C. Su, and J. Chen, "Analysis of application of the I _DDQ technique to the deep sub-micron VLSI testing," J. Electron. Test., vol. 18, no. 1, pp. 89-97, Feb. 2002.

Digital Library

[33]

{33} P. C. Maxwell and R. C. Aitken, "I _DDQ testing as a component of test suite: The need for several fault coverage metrics," J. Electron. Test.: Theory Appl., vol. 3, no. 4, pp. 305-316, Dec. 1992.

Digital Library

[34]

{34} A. D. Singh, "A Comprehensive wafer oriented test evaluation (WOTE) scheme for the I _DDQ testing of deep sub-micron technologies," in Proc. IEEE Int. Workshop I _DDQ Test., 1997, pp. 40-43.

Digital Library

[35]

{35} L. Rao, M. L. Bushnell, and V. Agrawal, "New I _DDQ signatures reduce defect level and yield loss," in Proc. North Atlantic Test Workshop, 2002, pp. 45-55.

[36]

{36} L. Rao, M. L. Bushnell, and V. Agrawal, "I _DDQ signatures reduce defect level and yield loss," in Proc. Int. Conf. VLSI Des., 2003, pp. 353-360.

Digital Library

[37]

{37} L. Rao, "Graphical CMOS IDDQ testing signatures based on data mining," Ph.D. dissertation, Electr. Comput. Eng. Dept., Rutgers Univ. Piscataway, NJ, 2003.

Digital Library

[38]

{38} L. Rao and M. L. Bushnell, "Graphical I _DDQ signatures for ULSI testing," U.S. Patent 6812724, Nov. 2, 2004.

[39]

{39} K. Fukunaga, Introduction to Statistical Pattern Recognition. San Francisco, CA: Morgan Kaufmann, 1990.

Digital Library

[40]

{40} V. D. Agrawal, "Sampling techniques for determining fault coverage in LSI circuits," J. Digit. Syst., vol. V, no. 3, pp. 189-202, 1981.

[41]

{41} M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. Boston, MA: Springer, 2000.

[42]

{42} K. Trivedi, Probability and Statistics With Reliability, Queuing and Computer Science Applications. Englewood-Cliffs, NJ: Prentice-Hall, 1982.

Digital Library

[43]

{43} J. van Sas, U. Swerts, and M. Darquennes, "Towards an effective I _DDQ test vector selection and application methodology," in Proc. Int. Test Conf., 1996, pp. 491-500.

Digital Library

Cited By

Chowdhury PGuin USingh AAgrawal V(2021)Estimating Operational Age of an Integrated CircuitJournal of Electronic Testing: Theory and Applications10.1007/s10836-021-05927-337:1(25-40)Online publication date: 1-Feb-2021
https://dl.acm.org/doi/10.1007/s10836-021-05927-3
Matakias STsiatouhas YArapoyanni AHaniotakis T(2015)A current monitoring technique for IDDQ testing in digital integrated circuitsIntegration, the VLSI Journal10.1016/j.vlsi.2015.01.00550:C(48-60)Online publication date: 1-Jun-2015
https://dl.acm.org/doi/10.1016/j.vlsi.2015.01.005

Index Terms

Graphical I_DDQ signatures reduce defect level and yield loss

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Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 15, Issue 11

November 2007

111 pages

ISSN:1063-8210

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Copyright © 2007.

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IEEE Educational Activities Department

United States

Publication History

Published: 01 November 2007

Received: 18 June 2004

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Cited By

Chowdhury PGuin USingh AAgrawal V(2021)Estimating Operational Age of an Integrated CircuitJournal of Electronic Testing: Theory and Applications10.1007/s10836-021-05927-337:1(25-40)Online publication date: 1-Feb-2021
https://dl.acm.org/doi/10.1007/s10836-021-05927-3
Matakias STsiatouhas YArapoyanni AHaniotakis T(2015)A current monitoring technique for IDDQ testing in digital integrated circuitsIntegration, the VLSI Journal10.1016/j.vlsi.2015.01.00550:C(48-60)Online publication date: 1-Jun-2015
https://dl.acm.org/doi/10.1016/j.vlsi.2015.01.005

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