Routing Techniques for Gate Array

This paper describes the routing techniques used for a Hughes internally developed high-density silicon-gate bulk CMOS gate array family. This layout software can be easily adapted to different array sizes and/or technologies (e.g., bipolar) through a change of parameters. A routing model and hierarchical decomposition schemes are presented to address the routability issue. More specifically, this paper focuses on the formulation and analysis of global routing and vertical assignment problems and gives a systematic breakdown of the routing task into well-defined subtasks. Instead of performing sequential routing, techniques and formulations are introduced to achieve a high degree of order independency in all subtasks. In routing subtasks where iterations are required, independent selection and interconnection are performed to avoid order dependency in typical routing problems. Implementation results are provided to indicate the efficiency of the system.