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research-article

Integer Multipliers with Overflow Detection

Authors:

Michael J. Schulte,

Mark G. ArnoldAuthors Info & Claims

IEEE Transactions on Computers, Volume 55, Issue 8

Pages 1062 - 1066

https://doi.org/10.1109/TC.2006.126

Published: 01 August 2006 Publication History

Abstract

This paper presents a general approach for designing array and tree integer multipliers with overflow detection. The overflow detection techniques are based on an analysis of the magnitudes of the input operands. The overflow detection circuits operate in parallel with a simplified multiplier to reduce the overall area and delay.

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Cited By

Tsai MFu YLiu JShi XWang BYang B(2023)Certified Verification for Algebraic AbstractionComputer Aided Verification10.1007/978-3-031-37709-9_16(329-349)Online publication date: 17-Jul-2023
https://dl.acm.org/doi/10.1007/978-3-031-37709-9_16
Zolfagharinejad MKamal MAfzali-Khusha APedram M(2022)Posit Process Element for Using in Energy-Efficient DNN AcceleratorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2022.316551030:6(844-848)Online publication date: 1-Jun-2022
https://dl.acm.org/doi/10.1109/TVLSI.2022.3165510
Gök MÖzbilen M(2018)Evaluation of Sticky-Bit Generation Methods for Floating-Point MultipliersJournal of Signal Processing Systems10.1007/s11265-008-0258-756:1(51-57)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1007/s11265-008-0258-7

Index Terms

Integer Multipliers with Overflow Detection
1. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Arithmetic and datapath circuits
      2. Combinational circuits
2. Mathematics of computing
  1. Mathematical analysis
    1. Numerical analysis
      1. Arbitrary-precision arithmetic
      2. Interval arithmetic

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 55, Issue 8

August 2006

141 pages

ISSN:0018-9340

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Copyright © 2006.

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IEEE Computer Society

United States

Publication History

Published: 01 August 2006

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Cited By

Tsai MFu YLiu JShi XWang BYang B(2023)Certified Verification for Algebraic AbstractionComputer Aided Verification10.1007/978-3-031-37709-9_16(329-349)Online publication date: 17-Jul-2023
https://dl.acm.org/doi/10.1007/978-3-031-37709-9_16
Zolfagharinejad MKamal MAfzali-Khusha APedram M(2022)Posit Process Element for Using in Energy-Efficient DNN AcceleratorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2022.316551030:6(844-848)Online publication date: 1-Jun-2022
https://dl.acm.org/doi/10.1109/TVLSI.2022.3165510
Gök MÖzbilen M(2018)Evaluation of Sticky-Bit Generation Methods for Floating-Point MultipliersJournal of Signal Processing Systems10.1007/s11265-008-0258-756:1(51-57)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1007/s11265-008-0258-7

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