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10.1109/ICCD.2005.50guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
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Error-tolerance memory Microarchitecture via Dynamic Multithreading

Published: 02 October 2005 Publication History

Abstract

Presented in this paper is an error-tolerance multithreaded register file microarchitecture that employs dynamicmultithreading redundancy for error control. The proposed technique is based on the observation that concurrent threads may not access a register entry simultaneously. The non-overlappedregister access patterns create hardware redundancy dynamically that can be exploited for error control. This significantly improves access time during error recovery. Simulation results of a generic simultaneous multithreading processor on the SPEC CPU2000 benchmark programs demonstrate 13.8% to 50.7% reduction in register read access overheads subject to 2% hardware overheads. The proposed error-tolerance memory microarchitecture features good scalability micro processor generations, where soft errors are expected to get worse with semiconductor process scaling.

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  • (2019)Improving error tolerance for multithreaded register filesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.5555/1515827.151583416:8(1009-1020)Online publication date: 21-Nov-2019

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cover image Guide Proceedings
ICCD '05: Proceedings of the 2005 International Conference on Computer Design
October 2005
699 pages
ISBN:0769524516

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IEEE Computer Society

United States

Publication History

Published: 02 October 2005

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  • (2019)Improving error tolerance for multithreaded register filesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.5555/1515827.151583416:8(1009-1020)Online publication date: 21-Nov-2019

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