Impact of Instruction Cache and Different Instruction Scratchpads on the WCET Estimate
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WCET-centric partial instruction cache locking
DAC '12: Proceedings of the 49th Annual Design Automation ConferenceCaches play an important role in embedded systems by bridging the performance gap between high speed processors and slow memory. At the same time, caches introduce imprecision in Worst-case Execution Time (WCET) estimation due to unpredictable access ...
WCET-Based Comparison of an Instruction Scratchpad and a Method Cache
ISORC '14: Proceedings of the 2014 IEEE 17th International Symposium on Object/Component-Oriented Real-Time Distributed ComputingThis paper compares two proposed alternatives to conventional instruction caches: a scratchpad memory (SPM) and a method cache. The comparison considers the true worst-case execution time (WCET) and the estimated WCET bound of programs using either an ...
WCET analysis of instruction cache hierarchies
With the advent of increasingly complex hardware in real-time embedded systems (processors with performance enhancing features such as pipelines, caches, multiple cores), most embedded processors use a hierarchy of caches. While much research has been ...
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