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10.1109/HPCC.2012.212guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
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An Analysis of the Impact of Bus Contention on the WCET in Multicores

Published: 25 June 2012 Publication History

Abstract

The use of multicores is becoming widespread in the field of embedded systems, many of which have real-time requirements. Hence, ensuring that real-time applications meet their timing constraints is a pre-requisite before deploying them on these systems. This necessitates the consideration of the impact of the contention due to shared low-level hardware resources like the front-side bus (FSB) on the Worst-Case Execution Time (WCET) of the tasks. Towards this aim, this paper proposes a method to determine an upper bound on the number of bus requests that tasks executing on a core can generate in a given time interval. We show that our method yields tighter upper bounds in comparison with the state-of-the-art. We then apply our method to compute the extra contention delay incurred by tasks, when they are co-scheduled on different cores and access the shared main memory, using a shared bus, access to which is granted using a round-robin arbitration (RR) protocol.

Cited By

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  • (2024)ITER: an ITERative approach for inter-core timing analysis in statically scheduled cyclic executive systems on COTS multicore platforms for CRTESThe Journal of Supercomputing10.1007/s11227-024-06208-480:13(19719-19770)Online publication date: 1-Sep-2024
  • (2022)Schedulability analysis for 3-phase tasks with partitioned fixed-priority schedulingJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2022.102706131:COnline publication date: 1-Oct-2022
  • (2022)Bus-contention aware WCRT analysis for the 3-phase task model considering a work-conserving bus arbitration schemeJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2021.102345122:COnline publication date: 1-Jan-2022
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  1. An Analysis of the Impact of Bus Contention on the WCET in Multicores

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    Published In

    cover image Guide Proceedings
    HPCC '12: Proceedings of the 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems
    June 2012
    1821 pages
    ISBN:9780769547497

    Publisher

    IEEE Computer Society

    United States

    Publication History

    Published: 25 June 2012

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    View all
    • (2024)ITER: an ITERative approach for inter-core timing analysis in statically scheduled cyclic executive systems on COTS multicore platforms for CRTESThe Journal of Supercomputing10.1007/s11227-024-06208-480:13(19719-19770)Online publication date: 1-Sep-2024
    • (2022)Schedulability analysis for 3-phase tasks with partitioned fixed-priority schedulingJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2022.102706131:COnline publication date: 1-Oct-2022
    • (2022)Bus-contention aware WCRT analysis for the 3-phase task model considering a work-conserving bus arbitration schemeJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2021.102345122:COnline publication date: 1-Jan-2022
    • (2019)A Survey of Timing Verification Techniques for Multi-Core Real-Time SystemsACM Computing Surveys10.1145/332321252:3(1-38)Online publication date: 18-Jun-2019
    • (2017)Tightening Contention Delays While Scheduling Parallel Applications on Multi-core ArchitecturesACM Transactions on Embedded Computing Systems10.1145/312649616:5s(1-20)Online publication date: 27-Sep-2017
    • (2014)Experiences with modeling memory contention for multi-core industrial real-time systemsProceedings of the 10th international ACM Sigsoft conference on Quality of software architectures10.1145/2602576.2602584(43-52)Online publication date: 27-Jun-2014

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