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A Scalable High-Performance Computing Solution for Networks on Chips

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Martti ForsellAuthors Info & Claims

IEEE Micro, Volume 22, Issue 5

Pages 46 - 55

https://doi.org/10.1109/MM.2002.1044299

Published: 01 September 2002 Publication History

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Abstract

The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs.

References

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Cited By

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Forsell MNikula SRoivainen JLeppänen VTräff J(2022)Performance and programmability comparison of the thick control flow architecture and current multicore processorsThe Journal of Supercomputing10.1007/s11227-021-03985-078:3(3152-3183)Online publication date: 1-Feb-2022
https://dl.acm.org/doi/10.1007/s11227-021-03985-0
Forsell MRoivainen JLeppänen V(2018)REPLICA MBTACThe Journal of Supercomputing10.1007/s11227-017-2199-z74:5(1911-1933)Online publication date: 1-May-2018
https://dl.acm.org/doi/10.1007/s11227-017-2199-z
Forsell MLeppänen VPenttonen M(2015)Cost of Bandwidth-Optimized Sparse Mesh LayoutsProceedings of the 13th International Conference on Parallel Computing Technologies - Volume 925110.1007/978-3-319-21909-7_37(375-389)Online publication date: 31-Aug-2015
https://dl.acm.org/doi/10.1007/978-3-319-21909-7_37
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Published In

IEEE Micro Volume 22, Issue 5

September 2002

88 pages

ISSN:0272-1732

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 September 2002

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Forsell MNikula SRoivainen JLeppänen VTräff J(2022)Performance and programmability comparison of the thick control flow architecture and current multicore processorsThe Journal of Supercomputing10.1007/s11227-021-03985-078:3(3152-3183)Online publication date: 1-Feb-2022
https://dl.acm.org/doi/10.1007/s11227-021-03985-0
Forsell MRoivainen JLeppänen V(2018)REPLICA MBTACThe Journal of Supercomputing10.1007/s11227-017-2199-z74:5(1911-1933)Online publication date: 1-May-2018
https://dl.acm.org/doi/10.1007/s11227-017-2199-z
Forsell MLeppänen VPenttonen M(2015)Cost of Bandwidth-Optimized Sparse Mesh LayoutsProceedings of the 13th International Conference on Parallel Computing Technologies - Volume 925110.1007/978-3-319-21909-7_37(375-389)Online publication date: 31-Aug-2015
https://dl.acm.org/doi/10.1007/978-3-319-21909-7_37
Girão GSantini TWagner FMacii E(2013)Exploring resource mapping policies for dynamic clustering on NoC-based MPSoCsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485454(681-684)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485454
Mäkelä JLeppänen VForsell M(2013)Towards a parallel debugging framework for the massively multi-threaded, step-synchronous REPLICA architectureProceedings of the 14th International Conference on Computer Systems and Technologies10.1145/2516775.2516818(153-160)Online publication date: 28-Jun-2013
https://dl.acm.org/doi/10.1145/2516775.2516818
Mäkelä JLeppänen VForsell M(2012)Preliminary analysis of feasible benchmark problems for the hydrid PRAM/NUMA REPLICA architectureProceedings of the 13th International Conference on Computer Systems and Technologies10.1145/2383276.2383283(37-44)Online publication date: 22-Jun-2012
https://dl.acm.org/doi/10.1145/2383276.2383283
Girão GSantini TWagner FPalesi MKumar S(2011)Dynamic clustering for distinct parallel programming models on NoC-based MPSoCsProceedings of the 4th International Workshop on Network on Chip Architectures10.1145/2076501.2076514(63-68)Online publication date: 4-Dec-2011
https://dl.acm.org/doi/10.1145/2076501.2076514
Mäkelä JLeppänen VForsell M(2011)RISC-based moving threads multicore architectureProceedings of the 12th International Conference on Computer Systems and Technologies10.1145/2023607.2023617(51-56)Online publication date: 16-Jun-2011
https://dl.acm.org/doi/10.1145/2023607.2023617
Leppänen VPenttonen MForsell M(2011)A layout for sparse cube-connected-cycles networkProceedings of the 12th International Conference on Computer Systems and Technologies10.1145/2023607.2023614(32-37)Online publication date: 16-Jun-2011
https://dl.acm.org/doi/10.1145/2023607.2023614
Oliveira BKreutz MCorrêa ESilva IMartino JAraújo GOrailoglu AKlein F(2010)Exploring memory organization in virtual MP-SoC platformsProceedings of the 23rd symposium on Integrated circuits and system design10.1145/1854153.1854175(79-84)Online publication date: 6-Sep-2010
https://dl.acm.org/doi/10.1145/1854153.1854175
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SAMBA-bus: A high performance bus architecture for system-on-chips

Networks on chips: structure and design methodologies

Synthesis of networks on chips for 3D systems on chips

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