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SAMBA-bus: A high performance bus architecture for system-on-chips

Authors:

Cheng-Kok KohAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 15, Issue 1

Pages 69 - 79

https://doi.org/10.1109/TVLSI.2007.891091

Published: 01 January 2007 Publication History

Abstract

A high performance communication architecture, SAMBA-bus, is proposed in this paper. In SAMBA-bus architecture, multiple compatible bus transactions can be performed simultaneously with only a single bus access grant from the bus arbiter. Experimental results show that, compared with a traditional bus architecture, the SAMBA-bus architecture can have up to 3.5 times improvement in the effective bandwidth, and up to 15 times reduction in the average communication latency. In addition, the performance of SAMBA-bus architecture is affected only slightly by arbitration latency, because bus transactions can be performed without waiting for the bus access grant from the arbiter. This feature is desirable in SoC designs with large numbers of modules and long communication delay between modules and the bus arbiter.

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Cited By

Cilardo AFusella E(2016)Design automation for application-specific on-chip interconnectsIntegration, the VLSI Journal10.1016/j.vlsi.2015.07.01752:C(102-121)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1016/j.vlsi.2015.07.017
Chung HTeuscher CPande P(2014)Design and Evaluation of Technology-Agnostic Heterogeneous Networks-on-ChipACM Journal on Emerging Technologies in Computing Systems10.1145/256766610:3(1-27)Online publication date: 6-May-2014
https://dl.acm.org/doi/10.1145/2567666
Oh JZajic APrvulovic MFensch CO'Boyle MSeznec ABodin F(2013)Traffic steering between a low-latency unswitched TL ring and a high-throughput switched on-chip interconnectProceedings of the 22nd international conference on Parallel architectures and compilation techniques10.5555/2523721.2523764(309-318)Online publication date: 7-Oct-2013
https://dl.acm.org/doi/10.5555/2523721.2523764
Show More Cited By

Index Terms

SAMBA-bus: A high performance bus architecture for system-on-chips
1. Hardware

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Information & Contributors

Information

Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 15, Issue 1

January 2007

124 pages

ISSN:1063-8210

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Copyright © 2007.

Publisher

IEEE Educational Activities Department

United States

Publication History

Published: 01 January 2007

Revised: 21 June 2006

Received: 05 October 2005

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Cited By

Cilardo AFusella E(2016)Design automation for application-specific on-chip interconnectsIntegration, the VLSI Journal10.1016/j.vlsi.2015.07.01752:C(102-121)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1016/j.vlsi.2015.07.017
Chung HTeuscher CPande P(2014)Design and Evaluation of Technology-Agnostic Heterogeneous Networks-on-ChipACM Journal on Emerging Technologies in Computing Systems10.1145/256766610:3(1-27)Online publication date: 6-May-2014
https://dl.acm.org/doi/10.1145/2567666
Oh JZajic APrvulovic MFensch CO'Boyle MSeznec ABodin F(2013)Traffic steering between a low-latency unswitched TL ring and a high-throughput switched on-chip interconnectProceedings of the 22nd international conference on Parallel architectures and compilation techniques10.5555/2523721.2523764(309-318)Online publication date: 7-Oct-2013
https://dl.acm.org/doi/10.5555/2523721.2523764
Chiu JYang KWong C(2012)Analytical modeling for multi-transaction bus on distributed systemsProceedings of the 12th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II10.1007/978-3-642-33065-0_1(1-9)Online publication date: 4-Sep-2012
https://dl.acm.org/doi/10.1007/978-3-642-33065-0_1

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