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research-article

Deep Submicron CMOS Current IC Testing: Is There a Future?

Published: 01 October 1999 Publication History

Abstract

First Page of the Article

References

[1]
S. Thompson, et al, "MOS Scaling: Transistor Challenges for the 21st Century," Intel Tech. J., no. 3, 1998.
[2]
H.-S.P. Wong, et al, "Nanoscale CMOS," Proc. IEEE, Apr. 1999.
[3]
A. Keshavarzi, et al, "Intrinsic Leakage in Low Power Deep Submicron CMOS ICs," Int'l Test Conf., 1997.
[4]
K. Baker, et al., "Defect-Based Delay Testing of Resistive Via-Contacts—a Critical Evaluation," Int'l Test Conf., 1999.
[5]
H. Hao and E. McCluskey, "Detecting Flaws by Very-Low-Voltage Testing," Int'l Test Conf., Atlantic City, N.J., 1998.
[6]
P. Maxwell, et al., "Current Ratios: A Self-Scaling Implementation Current Signatures for Production I DDQ Testing," Int'l Test Conf., Atlantic City, N.J., 1999.
[7]
T. Miller, "I DDQ Testing in Deep-Submicron Integrated Circuits," Int'l Test Conf., Atlantic City, N.J., 1999.
[8]
C. Thibeault, "A Histogram-Based Procedure for Current Testing of Active Defects," Int'l Test Conf., Atlantic City, N.J., 1999.
[9]
S. Jandhyala, et al., "Clustering-Based Techniques for I DDQ Testing," Int'l Test Conf., Atlantic City, N.J., 1999.
[10]
B. Kruseman, et al., "Transient Current Testing in 0.25 μm CMOS Devices," Int'l Test Conf., Atlantic City, N.J., 1999.

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    Information & Contributors

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    Published In

    cover image IEEE Design & Test
    IEEE Design & Test  Volume 16, Issue 4
    October 1999
    110 pages

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    IEEE Computer Society Press

    Washington, DC, United States

    Publication History

    Published: 01 October 1999

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