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An efficient channel clustering and flow rate allocation algorithm for non-uniform microfluidic cooling of 3D integrated circuits

Published: 01 January 2013 Publication History

Abstract

Heat removal problem has been a bane of three dimensional integrated circuits (3DICs). Comparing with other passive cooling techniques, microfluidic cooling appears to be an ideal cooling solution due to its high thermal conductivity and scalability. Without regarding to the fact of non-uniform power distribution of integrated circuits, existing microfluidic cooling with uniform cooling effort incurs large thermal gradient and wastes pump power. This can be avoided by the customized non-uniform cooling scheme proposed in this paper. The microfluidic channels are divided into clusters of relatively homogeneous power distribution and an appropriate flow rate setting is applied to each cluster based on the total flow rate and the maximum allowable temperature of the 3DIC. This paper proposes an efficient clustering algorithm to guide the division of microchannels into clusters and the allocation of cooling resources to each cluster in order to achieve an effective microfluidic cooling with minimal total flow rate. A compact steady state thermal simulator has been developed and verified. Supported by this fast and accurate thermal model, the proposed cooling method and clustering algorithm have been applied to a 3D multi-core testbench for simulation. Compared to the uniform flow rate cooling, the maximum temperature and thermal gradient were reduced under the same total flow rate settings. On the other hand, for a specific peak temperature constraint, up to 21.8% saving in total flow rate with moderate thermal gradients is achieved by the proposed clustered microfluidic cooling.

References

[1]
Jacob, P., Mitigating memory wall effects in high-clock-rate and multicore CMOS 3-D processor memory stacks. Proceedings of the IEEE. v97 i1. 108-122.
[2]
L.P. Carloni, P. Pande, Y. Xie, Networks-on-chip in emerging interconnect paradigms: advantages and challenges, in: Proceedings of the Third ACM/IEEE International Symposium on Networks-on-Chip, San Diego, California, 10-13 May 2009, pp. 93-102.
[3]
Y. Ye, et al., 3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC), in: Proceedings of the IEEE International Conference on 3D System Integration (3DIC), San Francisco, California, 28-30 September 2009, pp. 1-6.
[4]
Feero, B. and Pande, P., Networks-on-chip in a three-dimensional environment: a performance evaluation. IEEE Transactions on Computers. v58 i1. 32-45.
[5]
Y.F. Tsai, Y. Xie, N. Vijaykrishnan, M.J. Irwin, Three-dimensional cache design exploration using 3DCacti, in: Proceedings of the IEEE International Conference on Computer Design (ICCD), San Jose, California, 2-5 October 2005, pp. 519-524.
[6]
Processor design in 3D die-stacking technologies. IEEE Micro. v27 i3. 31-48.
[7]
H. Hua, et al., Exploring compromises among timing, power and temperature in three-dimensional integrated circuits, in: Proceedings of Design Automation Conference, San Francisco, California, 24-28 July 2006, pp. 997-1002.
[8]
Burns, J.A., A wafer-scale 3-D circuit integration technology. IEEE Transactions on Electron Devices. v53 i10. 2507-2516.
[9]
A.P. Karmarkar, X. Xu, V. Moroz, Performance and reliability analysis of 3D-integration structures employing Through Silicon Via (TSV), in: Proceedings of 2009 IEEE International Reliability Physics Symposium, Montreal, Canada, 26-30 April 2009, pp. 682-687.
[10]
E. Culurciello, A.G. Andreou, Capacitive coupling of data and power for 3D silicon-on-insulator VLSI, in: Proceedings of 2005 IEEE International Symposium on Circuits and Systems, vol. 4, Kobe, Japan, 23-26 May 2005, pp. 4142-4145.
[11]
M. Scandiuzzo, et al., 3D system on chip memory interface based on modeled capacitive coupling interconnections, in: Proceedings of 2010 IEEE International Conference on 3D Systems Integration Conference (3DIC), Munich, Germany, 16-18 November 2010, pp. 1-4.
[12]
D. Brooks, M. Martonosi, Dynamic thermal management for high-performance microprocessors, in: IEEE International Symposium on High-Performance Computing Architecture, Monterrey, Nuevo Leon, Mexico, 19-24 January 2001, pp. 171-182.
[13]
Liao, W.P., He, L. and Lepak, K.M., Temperature and supply voltage aware performance and power modeling at microarchitecture level. IEEE Transactions on CAD of Integrated Circuits and Systems. v24 i7. 1042-1053.
[14]
J. Donald, M. Martonosi, Techniques for multi-core thermal management: classification and new exploration, in: Proceedings of IEEE International Symposium of Computer Architecture, Boston, Massachusetts, 17-21 June 2006, pp. 78-88.
[15]
Kumar, A., Shang, L., Peh, L.-S. and Jha, N.K., System-level dynamic thermal management for high-performance microprocessors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. v27 i1. 96-108.
[16]
T. Ebi, M. Abdullah, A. Faruque, J. Henkel, TAPE: thermal-aware agent-based power economy for multi/many-core architecture, in: Proceedings of IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, 2-5 November 2009, pp. 302-309.
[17]
M.S. Bakir, B. Dang, J.D. Meindl, Revolutionary nanosilicon ancillary technologies for ultimate-performance gigascale systems, in: Proceedings of Custom Integrated Circuits Conference, San Jose, California, 16-19 September 2007, pp. 421-428.
[18]
Yu, H., Shi, Y., He, L. and Karnik, T., Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. IEEE Transactions on Very Large Integrated Circuits and Systems. v16 i12. 1609-1619.
[19]
Yu, H., Ho, J. and He, L., Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity. ACM Transactions on Design Automation of Electronic Systems. v14 i3. 1-31.
[20]
J. Cong, Y. Zhang, Thermal via planning for 3-D ICs, in: Proceedings of IEEE/ACM International Symposium Computer-Aided Design, San Jose, California, 6-10 November 2005, pp. 744-751.
[21]
T. Zhang, Y. Zhang, S. Sapatnekar, Temperature-aware routing in 3-D ICs, in: Proceedings of IEEE Asia South Pacific Design Automation Conference, Yokohama, Japan, 24-27 January 2006, pp. 309-314.
[22]
Tuckerman, D.B. and Pease, R.F.W., High-performance heat sinking for VLSI. IEEE Electron Device Letters. vEDL-2 i5.
[23]
Koo, J.M., Im, S.J., Jiang, L. and Goodson, K.E., Integrated microchannel cooling for three-dimensional electronic circuit architectures. Journal of Heat Transfer (Transactions of the ASME). v127 i1. 49-58.
[24]
Kim, Y.J., Thermal characterization of interlayer microfluidic cooling of three-dimensional integrated circuits with nonuniform heat flux. Journal of Heat Transfer (Transactions of the ASME). v132 i4. 1-9.
[25]
B.B. Dang, et al., Wafer-level microfluidic cooling interconnects for GSI, in: Proceedings of the IEEE International Interconnect Technology Conference, San Francisco, California, 6-8 June 2005, pp. 180-182.
[26]
A.K. Coskun, et al., Energy-efficient variable-flow liquid cooling in 3D stacked architectures, in: Design, Automation and Test in Europe Conference, Dresden, Germany, 8-12 March 2010, pp. 111-116.
[27]
Y.J. Lee, R. Goel, S.K. Lim, Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs, in: Proceedings 2009 IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, 2-5 November 2009, pp. 645-651.
[28]
H. Mizunuma, C.-L. Yang, Y.-C. Lu, Thermal modeling for 3D-ICs with integrated microchannel cooling, in: Proceedings of 2009 IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, 2-5 November 2009, pp. 256-263.
[29]
A. Sridhar, et al., 3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling, in: Proceedings of 2010 IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, 7-11 November 2010, pp. 463-470.
[30]
A. Sridhar, et al., Compact transient thermal model for 3D ICs with liquid cooling via enhanced heat transfer cavity geometries, in: Sixteenth International Workshop on Thermal Investigations of ICs and Systems (THERMINIC), Barcelona, Spain, October 2010, pp. 1-6.
[31]
Sobhan, C.B. and Garimella, S.V., A comparative analysis of studies on heat transfer and fluid flow in microchannels. Microscale Thermophysical Engineering. v5 i4. 293-311.
[32]
B. Amelifard, A. Afzali-Kusha, A. Khadernzadeh, Enhancing the efficiency of cluster voltage scaling technique for low-power application, in: Proceedings of 2005 IEEE International Symposium on Circuits and Systems, vol. 2, Kobe, Japan, 23-26 May 2005, pp. 1666-1669.
[33]
Qian, H., Huang, X., Yu, H. and Chang, C.H., Cyber-physical thermal management of 3D multi-core cache processor system with microfluidic cooling. ASP Journal of Low Power Electronics. v7 i1. 110-121.
[34]
Kaminski, D.A. and Jensen, M.K., Introduction to Thermal and Fluids Engineering. 2005. John Wiley & Sons, Inc.
[35]
Peng, X.F. and Peterson, G.P., Convective heat transfer and flow friction for water flow in microchannel structures. International Journal of Heat Mass Transfer. v39 i12. 2599-2608.
[36]
Seider, E.N. and Tate, G.E., Heat transfer and pressure drop of liquids in tubes. Industrial & Engineering Chemistry. v28 i12. 1429-1435.
[37]
M.M. Sabry, A.K. Coskun, D. Atienza, Fuzzy control for enforcing energy efficiency in high-performance 3D systems, in: Proceedings of 2010 IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, 7-11 November 2010, pp. 642-648.
[38]
Oertel, H., Prandtl-Essentials of Fluid Mechanics. 2009. Springer.
[39]
CurieJet Piezoelectric Micropump {http://www.microjet.com.tw/}.
[40]
ASCO miniature valves {http://www.ascovalve.com/}.
[41]
Wattch {http://www.eecs.harvard.edu/~dbrooks/wattch-form.html}.
[42]
COMSOL Multiphysics {http://www.comsol.com}.
[43]
T.A. Davis, E. Palamadai, KLU: Sparse LU Factorization Algorithm for Circuit Simulation {http://www.cise.ufl.edu/research/sparse/klu/}.
[44]
T.A. Davis, SuiteSparse: Collection of Packages for Sparse Matrix Algorithms {http://www.cise.ufl.edu/research/sparse/SuiteSparse/}.
[45]
SPEC2000: Standard Performance Evaluation Corporation {http://www.spec.org/cpu2000/}.
[46]
HotSpot {http://lava.cs.virginia.edu/HotSpot/}.

Cited By

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  • (2018)Design Optimization of 3D Multi-Processor System-on-Chip with Integrated Flow Cell ArraysProceedings of the International Symposium on Low Power Electronics and Design10.1145/3218603.3218606(1-6)Online publication date: 23-Jul-2018
  • (2017)Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network DesignProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062285(1-6)Online publication date: 18-Jun-2017
  • (2015)Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal StructureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.232118223:4(731-742)Online publication date: 1-Apr-2015

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Information & Contributors

Information

Published In

cover image Integration, the VLSI Journal
Integration, the VLSI Journal  Volume 46, Issue 1
January, 2013
88 pages

Publisher

Elsevier Science Publishers B. V.

Netherlands

Publication History

Published: 01 January 2013

Author Tags

  1. 3DIC
  2. Channel cluster
  3. Clustered cooling effort
  4. Clustering algorithm
  5. Microfluidic cooling
  6. Thermal model

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View all
  • (2018)Design Optimization of 3D Multi-Processor System-on-Chip with Integrated Flow Cell ArraysProceedings of the International Symposium on Low Power Electronics and Design10.1145/3218603.3218606(1-6)Online publication date: 23-Jul-2018
  • (2017)Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network DesignProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062285(1-6)Online publication date: 18-Jun-2017
  • (2015)Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal StructureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.232118223:4(731-742)Online publication date: 1-Apr-2015

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