Thermal Effect of TSVs in 3D Die-Stacked Integrated Circuits

Shorter interconnects and higher integration are among the benefits that 3D die-stacking is expected to bring to future integrated circuits. However, when stacking power-dissipating dies one on top of the other, the total power density increases accordingly. As a result, temperatures in 3DICs are exacerbated. TSVs are regarded as a solution since they are made of copper and have a high thermal conductivity. In this paper, both the global and the local thermal effects of TSVs are evaluated by means of a framework based on FEM. By using a TSV grid covering a whole IC, it is shown that, on a global scale, TSVs make the overall average temperature drop slightly. Furthermore, on a local scale, it is shown that the insertion of TSVs near a hotspot has an effect that not only depends on the density of the TSVs but also on how they are arranged. Our experiments have also revealed that other parameters, such as the thermal conductivity of the material in which the hotspot is located, may influence the cooling efficiency of the TSVs.