[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
research-article

Biologically compatible neural networks with reconfigurable hardware

Published: 01 November 2015 Publication History

Abstract

This paper presents a reconfigurable hardware neuro-simulator specifically designed to emulate biophysically accurate and biologically compatible neural networks. The platform is based on FPGA technology which is used to create real-time custom neuroprocessors with floating point accuracy and a novel hybrid time-event driven architecture for synaptic integration. Through a series of experiments the dynamics of the neuroprocessors are evaluated and compared with real neuron responses. The problem of interconnecting neurons with individual synapses is tackled with a novel synaptic architecture where all incoming synapses are merged efficiently in one single accumulative process without losing biological information. The case studies demonstrate the suitability of conductance-based models and FPGA platforms to simulate living organisms' behaviour in a biological compatible context.

References

[1]
Dunn, N.A., Conery, J.S., Lockery, S.R., A neural network model for chemotaxis in Caenorhabditis elegans. Proceedings of the International Joint Conference on Neural Networks, 2003, vol. 4, 20-24 July 2003, pp. 2574-2578.
[2]
A. Stumpner, B. Ronacher, Neurophysiological aspects of song pattern-recognition and sound localization in grasshoppers, Am. Zool., 34 (1994) 696-705.
[3]
A. Scott, How smart is a neuron? A Review of Christof Koch's 'Biophysics of Computation', 2000.
[4]
A.V. Herz, T. Gollisch, C.K. Machens, D. Jaeger, Modeling single-neuron dynamics and computations: a balance of detail and abstraction, Science, 314 (2006) 80-85.
[5]
J. Mutch, U. Knoblich, T. Poggio, 2010. CNS: a GPU-based framework for simulating cortically-organized networks. (MIT-CSAIL-TR-2010-013/ CBCL-286).
[6]
M. Beuler, A. Tchaptchet, W. Bonath, S. Postnova, H. Braun, Real-time simulations of synchronization in a conductance-based neuronal network with a digital FPGA hardware-core, in: Artificial Neural Networks and Machine Learning - ICANN 2012, vol. 7552, Springer, Berlin Heidelberg, 2012, pp. 97-104.
[7]
K. Cheung, S. Schultz, W. Luk, A large-scale spiking neural network accelerator for FPGA systems, in: Artificial Neural Networks and Machine Learning - ICANN 2012, vol. 7552, Springer, Berlin Heidelberg, 2012, pp. 113-120.
[8]
Y. Zhang, J. Nunez, J. McGeehan, Biophysically Accurate Floating Point Neuroprocessors, University of Bristol, 2010.
[9]
G. Smaragdos, S. Isaza, M.F.v. Eijk, I. Sourdis, C. Strydis, FPGA-based biophysically-meaningful modeling of olivocerebellar neurons, in: Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ACM, Monterey, California, USA, 2014, pp. 89-98.
[10]
A. Kulakov, Multiprocessing Neural Network Simulator, PhD thesis, Faculty of Engineering and Applied Science, Department of Electronics and Computer Science, University of Southhampton, UK, 2012.
[11]
P.F. Pinsky, J. Rinzel, Intrinsic and network rhythmogenesis in a reduced Traub model for CA3 neurons, J. Comput. Neurosci., 2 (1995).
[12]
R.D. Traub, R.K. Wong, R. Miles, H. Michelson, A model of a CA3 hippocampal pyramidal neuron incorporating voltage-clamp data on intrinsic conductances, J. Neurophysiol., 66 (1991) 635-650.
[13]
B. Hille, Ionic Channels of Excitable Membranes, Sinauer Associates Inc., 1992.
[14]
S.W. Hughes, M. Lo¿rincz, D.W. Cope, V. Crunelli, NeuReal: an interactive simulation system for implementing artificial dendrites and large hybrid networks, J. Neurosci. Methods, 169 (2008) 290-301.
[15]
F.d. Dinechin, J. Detrey, O. Cret, R. Tudoran, When FPGAs are better at floating-point than microprocessors, in: Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays, ACM, Monterey, California, USA, 2008.
[16]
J.C. Moctezuma, J.P. McGeehan, J.L. Nunez-Yanez, Numerically efficient and biophysically accurate neuroprocessing platform, in: 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2013.
[17]
P.J. Fox, S.W. Moore, Efficient handling of synaptic updates in FPGA-based large-scale neural network simulations, in: Workshop on Neural Engineering using Reconfigurable Hardware 2012, 2012.
[18]
A. Destexhe, Z.F. Mainen, T.J. Sejnowski, An efficient method for computing synaptic conductances based on a kinetic-model of receptor-binding, Neural Comput., 6 (1994) 14-18.
[19]
H. Kager, W. Wadman, G. Somjen, Seizure-like afterdischarges simulated in a model neuron, J. Comput. Neurosci., 22 (2007) 105-128.
[20]
A.A. Hill, J. Lu, M. Masino, O. Olsen, R.L. Calabrese, A model of a segmental oscillator in the leech heartbeat neuronal network, J. Comput. Neurosci., 10 (2001) 281-302.
[21]
M. Ambroise, T. Levi, S. Saïghi, Leech heartbeat neural network on FPGA, in: Biomimetic and Biohybrid Systems, vol. 8064, Springer, Berlin Heidelberg, 2013, pp. 347-349.
[22]
M.A. Bhuiyan, A. Nallamuthu, M.C. Smith, V.K. Pallipuram, Optimization and performance study of large-scale biological networks for reconfigurable computing, in: High-Performance Reconfigurable Computing Technology and Applications (HPRCTA), 2010, pp. 1-9
[23]
S.W. Moore, P.J. Fox, S.J.T. Marsh, A.T. Markettos, A. Mujumdar, Bluehive - a field-programable custom computing machine for extreme-scale real-time neural network simulation, in: 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2012.
[24]
M. Mokhtar, D. Halliday, A. Tyrrell, Hippocampus-inspired spiking neural network on FPGA, in: Evolvable Systems: From Biology to Hardware, vol. 5216, Springer, Berlin Heidelberg, 2008, pp. 362-371.

Cited By

View all
  • (2019)Multi-objective Spiking Neural Network Hardware Mapping Based on Immune Genetic AlgorithmArtificial Neural Networks and Machine Learning – ICANN 2019: Theoretical Neural Computation10.1007/978-3-030-30487-4_58(745-757)Online publication date: 17-Sep-2019
  • (2018)Layered tile architecture for efficient hardware spiking neural networksMicroprocessors & Microsystems10.1016/j.micpro.2017.07.00553:C(21-32)Online publication date: 28-Dec-2018
  1. Biologically compatible neural networks with reconfigurable hardware

    Recommendations

    Comments

    Please enable JavaScript to view thecomments powered by Disqus.

    Information & Contributors

    Information

    Published In

    cover image Microprocessors & Microsystems
    Microprocessors & Microsystems  Volume 39, Issue 8
    November 2015
    718 pages

    Publisher

    Elsevier Science Publishers B. V.

    Netherlands

    Publication History

    Published: 01 November 2015

    Author Tags

    1. Biological compatible neurons
    2. Biophysically accurate model
    3. FPGA neuro-simulator
    4. Hardware neuro modelling
    5. Pinsky-Rinzel model

    Qualifiers

    • Research-article

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)0
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 17 Jan 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2019)Multi-objective Spiking Neural Network Hardware Mapping Based on Immune Genetic AlgorithmArtificial Neural Networks and Machine Learning – ICANN 2019: Theoretical Neural Computation10.1007/978-3-030-30487-4_58(745-757)Online publication date: 17-Sep-2019
    • (2018)Layered tile architecture for efficient hardware spiking neural networksMicroprocessors & Microsystems10.1016/j.micpro.2017.07.00553:C(21-32)Online publication date: 28-Dec-2018

    View Options

    View options

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media