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research-article

CLEAR: : Cache Lines Error Accumulation Reduction by exploiting invisible accesses

Authors:

Amir Mahdi Hosseini MonazzahAuthors Info & Claims

Volume 90, Issue C

Pages 123 - 132

https://doi.org/10.1016/j.mejo.2019.05.020

Published: 01 August 2019 Publication History

Abstract

SRAM caches are the most vulnerable processor component to radiation-induced soft errors. Error-Correcting Codes (ECCs) are the conventional scheme to protect caches against soft errors. These errors in the shape of Single-Event Upset (SEU), in which single bit or multiple adjacent bits are affected, can be correctable by ECCs. However, conventional ECCs are unable to correct temporal MBUs (Multiple-Bit Upset), in which two or more SEUs are accumulated in a data word over time. This paper proposes CLEAR (Cache Lines Error Accumulation Reduction) scheme to reduce the occurrence probability of temporal MBUs. By exploiting inherently available externally invisible accesses to all cache ways in a read request, CLEAR conducts more frequent ECC checking for each data word. Therefore, the ECC checking intervals are shortened, which leads to a significant reduction in occurrence probability of temporal MBUs. The evaluations show that CLEAR increases the Mean Time To Failure (MTTF) of the cache by more than 4× compared to the conventional cache architecture with negligible overheads.

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Cited By

Du XDong HYue H(2021)Cache Tag Array Fault Tolerance Method Based on Redundancy and Similarity of Adjacent Cache Line Tag BitsInternational Conference on Frontiers of Electronics, Information and Computation Technologies10.1145/3474198.3478212(1-8)Online publication date: 21-May-2021
https://dl.acm.org/doi/10.1145/3474198.3478212

Index Terms

CLEAR: Cache Lines Error Accumulation Reduction by exploiting invisible accesses
1. Hardware

Index terms have been assigned to the content through auto-classification.

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cover image Microelectronics Journal

Microelectronics Journal Volume 90, Issue C

Aug 2019

353 pages

ISSN:0026-2692

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Elsevier Ltd.

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Elsevier Science Publishers B. V.

Netherlands

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Published: 01 August 2019

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Cited By

Du XDong HYue H(2021)Cache Tag Array Fault Tolerance Method Based on Redundancy and Similarity of Adjacent Cache Line Tag BitsInternational Conference on Frontiers of Electronics, Information and Computation Technologies10.1145/3474198.3478212(1-8)Online publication date: 21-May-2021
https://dl.acm.org/doi/10.1145/3474198.3478212

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