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Efficient signed-digit-to-canonical-signed-digit recoding circuits

Author:

Yuuki TanakaAuthors Info & Claims

Microelectronics Journal, Volume 57, Issue C

Pages 21 - 25

https://doi.org/10.1016/j.mejo.2016.09.001

Published: 01 November 2016 Publication History

Abstract

In this study, we propose a new signed-digit-to-canonical-signed-digit recoding circuit based on parallel prefix structures. Several articles have been devoted to the study of canonical signed-digit recoding circuits. However, most of those re-code from 2's complement binary number representation. Unlike those, our proposed architectures convert from signed-digit number representation. The circuit structure is somewhat different from those in previous articles, because each digit in the input is accompanied by its sign. We evaluate the proposed circuit and compare it with a circuit based on the conditional sum structure. We show that the proposed architectures performs faster by 30% or more than the circuit based on the conditional sum structure.

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Cited By

Nahvy ANavabi Z(2024)Pico-Programmable Neurons to Reduce Computations for Deep Neural Network AcceleratorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.338669832:7(1216-1227)Online publication date: 1-Jul-2024
https://dl.acm.org/doi/10.1109/TVLSI.2024.3386698
Yu PPonzina FLevisse AGupta MBiswas DAnsaloni GAtienza DCatthoor F(2024)An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.337579332:6(1018-1031)Online publication date: 25-Mar-2024
https://dl.acm.org/doi/10.1109/TVLSI.2024.3375793
Mora HSignes-Pont MJimeno-Morenilla ASánchez-Romero J(2019)High-performance architecture for digital transform processingThe Journal of Supercomputing10.1007/s11227-018-2436-075:3(1336-1349)Online publication date: 1-Mar-2019
https://dl.acm.org/doi/10.1007/s11227-018-2436-0

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Information

Published In

cover image Microelectronics Journal

Microelectronics Journal Volume 57, Issue C

November 2016

57 pages

ISSN:0026-2692

Issue’s Table of Contents

Copyright © Elsevier Ltd.

Publisher

Elsevier Science Publishers B. V.

Netherlands

Publication History

Published: 01 November 2016

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Cited By

Nahvy ANavabi Z(2024)Pico-Programmable Neurons to Reduce Computations for Deep Neural Network AcceleratorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.338669832:7(1216-1227)Online publication date: 1-Jul-2024
https://dl.acm.org/doi/10.1109/TVLSI.2024.3386698
Yu PPonzina FLevisse AGupta MBiswas DAnsaloni GAtienza DCatthoor F(2024)An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.337579332:6(1018-1031)Online publication date: 25-Mar-2024
https://dl.acm.org/doi/10.1109/TVLSI.2024.3375793
Mora HSignes-Pont MJimeno-Morenilla ASánchez-Romero J(2019)High-performance architecture for digital transform processingThe Journal of Supercomputing10.1007/s11227-018-2436-075:3(1336-1349)Online publication date: 1-Mar-2019
https://dl.acm.org/doi/10.1007/s11227-018-2436-0
Palchaudhuri ADhar A(2019)Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding ImplementationsJournal of Electronic Testing: Theory and Applications10.1007/s10836-019-05840-w35:6(779-796)Online publication date: 1-Dec-2019
https://dl.acm.org/doi/10.1007/s10836-019-05840-w

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