[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
research-article

Dynamic Instruction Scheduling and the Astronautics ZS-1

Published: 01 July 1989 Publication History

Abstract

An overview of and survey solutions to the problem of instruction scheduling for pipelined computers are provided. The author demonstrated that dynamic instruction scheduling can provide performance improvements not possible with static scheduling alone. He describes a high-performance computer, the Astronautics ZS-1, which uses novel methods for implementing dynamic scheduling and which can outperform computers using similar-speed technologies that rely solely on state-of-the-art static scheduling techniques.

References

[1]
1. J. Hennessy, "VLSI Processor Architecture," IEEE Trans. on Computers, Vol. 33, Dec. 1984, pp. 1,221-1,246.
[2]
2. D.A. Patterson, "Reduced Instruction Set Computers," Comm. ACM, Vol. 28, Jan, 1985, pp. 8-21.
[3]
3. D.W. Clark, "Pipelining and Performance in the VAX 8800 Processor," Proc. 2nd Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Oct. 1987, pp. 173-177.
[4]
4. J.E. Thornton, Design of a Computer -- The Control Data 6600, Scott, Foresman and Co., Glenview, Ill., 1970.
[5]
5. D.W. Anderson, F.J. Sparacio, and R.M. Tomasulo, "The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling," IBM J. Research and Development , Jan. 1967, pp. 8-24.
[6]
6. R.M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM J. Research and Development, Jan. 1967, pp. 25-33.
[7]
7. J.A. Fisher, "Trace Scheduling: A Technique for Global Microcode Compaction," IEEE Trans. Computers, Vol. C-30, July 1981, pp. 478-490.
[8]
8. S. Weiss and J.E. Smith, "Instruction Issue Logic in Pipelined Supercomputers," IEEE Trans. Computers, Vol. C-33, Nov. 1984, pp. 1,013-1,022.
[9]
9. D.A. Padua and M.J. Wolfe, "Advanced Compiler Optimizations for Supercomputers," Comm. ACM, Vol. 29, Dec. 1986, pp. 1,184-1,201.
[10]
10. R.P. Colwell et al., "A VLIW Architecture for a Trace Scheduling Compiler," IEEE Trans. Computers, Vol. 37, Aug. 1988, pp. 967-979.
[11]
11. F.H. McMahon, "The Livermore Fortran Kernels: A Computer Test of the Numerical Performance Range," Research Report, Lawrence Livermore Laboratories, Dec. 1986.
[12]
12. L.J. Boland et al., "The IBM System/360 Model 91: Storage System," IBM J., Jan. 1967, pp. 54-68.
[13]
13. J.E. Smith, S. Weiss, and N. Pang, "A Simulation Study of Decoupled Architecture Computers," IEEE Trans. Computers, Vol. C-35, Aug. 1986, pp. 692-702.
[14]
14. J.E. Smith et al., "The ZS-1 Central Processor," Proc. ASPLOS II, Oct. 1987, pp. 199-204.
[15]
15. P.B. Schneck, Supercomputer Architectures , Kluwer Acacemic Publishers, Norwell, Mass., 1988.
[16]
16. P.M. Kogge, The Architecture of Pipelined Computers, McGraw-Hill, New York, 1981.
[17]
17. W. Hwu and Y.N. Patt, "HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality," Proc. 13th Ann. Symp. Computer Architecture , June 1986, pp. 297-307.

Cited By

View all
  • (2011)Computer Architecture, Fifth EditionundefinedOnline publication date: 29-Sep-2011
  • (2004)The Vector-Thread ArchitectureProceedings of the 31st annual international symposium on Computer architecture10.5555/998680.1006736Online publication date: 19-Jun-2004
  • (2004)The Vector-Thread ArchitectureACM SIGARCH Computer Architecture News10.1145/1028176.100673632:2(52)Online publication date: 2-Mar-2004
  • Show More Cited By

Recommendations

Reviews

Lanfranco Lopriore

Smith is a member of the project team for the Astronautics ZS-1. The ZS-1 is a high-speed computer system for scientific applications. It uses two instruction pipelines, one for fixed-point and memory addressing operations, the other for floating-point operations. A salient feature of the ZS-1 pipeline organization is that it reorders instructions at run time (dynamic instruction scheduling). Dynamic scheduling provides better performance and faster compilation than a reordering made by the software at compile time (static instruction scheduling). The paper's contribution is twofold: it accurately identifies the design problems behind pipelining and clearly presents possible implementations of the pipeline concept. The paper is organized into a well-structured set of case analyses, including studies of the CDC 6600, the IBM 360/91, and the ZS-1, whose architecture is described in particular depth. The paper is well written and carefully presented. I recommend it not only for the computer architect involved in a similar project, but also for the nonspecialist who wishes to become acquainted with a primary aspect of high-performance computer organization.

Access critical reviews of Computing literature here

Become a reviewer for Computing Reviews.

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image Computer
Computer  Volume 22, Issue 7
July 1989
94 pages
ISSN:0018-9162
Issue’s Table of Contents

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 July 1989

Qualifiers

  • Research-article

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)0
  • Downloads (Last 6 weeks)0
Reflects downloads up to 11 Dec 2024

Other Metrics

Citations

Cited By

View all
  • (2011)Computer Architecture, Fifth EditionundefinedOnline publication date: 29-Sep-2011
  • (2004)The Vector-Thread ArchitectureProceedings of the 31st annual international symposium on Computer architecture10.5555/998680.1006736Online publication date: 19-Jun-2004
  • (2004)The Vector-Thread ArchitectureACM SIGARCH Computer Architecture News10.1145/1028176.100673632:2(52)Online publication date: 2-Mar-2004
  • (2004)The Vector-Thread ArchitectureIEEE Micro10.1109/MM.2004.9024:6(84-90)Online publication date: 1-Nov-2004
  • (2004)Cache Refill/Access Decoupling for Vector MachinesProceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2004.9(331-342)Online publication date: 4-Dec-2004
  • (2001)Multithreading decoupled architectures for complexity-effective general purpose computingACM SIGARCH Computer Architecture News10.1145/563647.56365829:5(56-61)Online publication date: 1-Dec-2001
  • (1997)Superscalar Instruction IssueIEEE Micro10.1109/40.62121117:5(28-39)Online publication date: 1-Sep-1997
  • (1996)Hierarchical Execution to Speed Up Pipeline Interlock in Mainframe ComputersIEEE Transactions on Computers10.1109/12.50991045:5(589-599)Online publication date: 1-May-1996
  • (1996)ARBIEEE Transactions on Computers10.1109/12.50990745:5(552-571)Online publication date: 1-May-1996
  • (1994)POWER2 floating-point unitIBM Journal of Research and Development10.1147/rd.385.052538:5(525-536)Online publication date: 1-Sep-1994
  • Show More Cited By

View Options

View options

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media