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Article

Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program

Authors:

Vishwani D. Agrawal,

Michael L. BushnellAuthors Info & Claims

VLSID '03: Proceedings of the 16th International Conference on VLSI Design

Page 527

Published: 04 January 2003 Publication History

Abstract

In the previous work, the problem of finding gatedelays to eliminate glitches has been solved by linearprograms (LP) requiring an exponentially largenumber of constraints. By introducing two additionalvariables per gate, namely, the fastest and the slowestarrival times, besides the gate delay, we reduce thenumber of the LP constraints to be linear in circuitsize. For example, the 469-gate c880 circuit requires3,611 constraints as compared to the 6.95 million constraintsneeded with the previous method. The reducedconstraints provably produce the same exactLP solution as obtained by the exponential set of constraints.For the first time, we are able to optimize allISCAS'85 benchmarks. For the c7552 circuit, whenthe input to output delay is constrained not to increase,a design with 366 delay buffers consumes only34% peak and 38% average po er as compared toan unoptimized design. As shown in previous work,the use of delay buffers is essential in this case. Thepracticality of the design is demonstrated by implementingan optimized 4-bit ALU circuit for which thepower consumption as obtained by a circuit-levelsimulator.

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Cited By

Hu FAgrawal VNebel WStan MRaghunathan AHenkel JMarculescu D(2006)Input-specific dynamic power optimization for VLSI circuitsProceedings of the 2006 international symposium on Low power electronics and design10.1145/1165573.1165630(232-237)Online publication date: 4-Oct-2006
https://dl.acm.org/doi/10.1145/1165573.1165630
Raja TAgrawal VBushnell M(2005)Design of variable input delay gates for low dynamic power circuitsProceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/11556930_45(436-445)Online publication date: 21-Sep-2005
https://dl.acm.org/doi/10.1007/11556930_45
Lu YAgrawal V(2005)Leakage and dynamic glitch power minimization using integer linear programming for vth assignment and path balancingProceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/11556930_23(217-226)Online publication date: 21-Sep-2005
https://dl.acm.org/doi/10.1007/11556930_23

Index Terms

Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
1. Hardware
  1. Integrated circuits
    1. Interconnect
      1. Input / output circuits
  2. Very large scale integration design

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Information

Published In

cover image Guide Proceedings

VLSID '03: Proceedings of the 16th International Conference on VLSI Design

January 2003

ISBN:0769518680

Copyright © Copyright (c) 2003 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

Publisher

IEEE Computer Society

United States

Publication History

Published: 04 January 2003

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Cited By

Hu FAgrawal VNebel WStan MRaghunathan AHenkel JMarculescu D(2006)Input-specific dynamic power optimization for VLSI circuitsProceedings of the 2006 international symposium on Low power electronics and design10.1145/1165573.1165630(232-237)Online publication date: 4-Oct-2006
https://dl.acm.org/doi/10.1145/1165573.1165630
Raja TAgrawal VBushnell M(2005)Design of variable input delay gates for low dynamic power circuitsProceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/11556930_45(436-445)Online publication date: 21-Sep-2005
https://dl.acm.org/doi/10.1007/11556930_45
Lu YAgrawal V(2005)Leakage and dynamic glitch power minimization using integer linear programming for vth assignment and path balancingProceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/11556930_23(217-226)Online publication date: 21-Sep-2005
https://dl.acm.org/doi/10.1007/11556930_23

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