An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits

The availability of dual Vt CMOS process provides a practical way to achieve high performance and low leakage power dissipation for current deep sub-micron technology. Early work on leakage power optimization of digital circuits utilizing dual Vt devices show some promising results. However, due to the lack of real dual Vt process models and parameters, these works are based on simple power and delay analysis of dual Vt devices. For example, the impact of dual Vt on the short circuit power dissipation is ignored in all these works. In this paper we provide extensive HSPICE simulation results on CMOS gates and circuits from a commercial dual Vt CMOS process. The experimental results show that optimization of dual Vt circuits involves complex tradeoffs between leakage power, short circuit power and performance. For example, it is observed that using lower Vt devices does not always result in a faster circuit. One of the main contributions of this paper is that it reveals some new challenges and opportunities offered by the dual Vt technology to both circuits designers and CAD software developers for circuit optimization.