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Article

A Flexible Power Model for FPGAs

Authors:

Kara K. W. Poon,

Steven J. E. WiltonAuthors Info & Claims

FPL '02: Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications

Pages 312 - 321

Published: 02 September 2002 Publication History

Abstract

This paper describes a flexible power model for FPGAs. The model estimates the dynamic, short circuit, and leakage power for a wide variety of FPGA architectures. Such a model will be essential in the design and research of next-generation FPGAs, where power will be one of the primary optimization goals. The model has been integrated into the VPR CAD flow, and is available to the research community for use in FPGA architectural and CAD tool experimentation.

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Cited By

Leong PAmano HAnderson JBertels KCardoso JDiessel OGogniat GHutton MLee JLuk WLysaght PPlatzner MPrasanna VRissa TSilvano CSo HWang Y(2017)The First 25 Years of the FPL ConferenceACM Transactions on Reconfigurable Technology and Systems10.1145/299646810:2(1-17)Online publication date: 22-Mar-2017
https://dl.acm.org/doi/10.1145/2996468
Leow YAkoglu ALysecky S(2013)An Analytical Model for Evaluating Static Power of Homogeneous FPGA ArchitecturesACM Transactions on Reconfigurable Technology and Systems10.1145/25359356:4(1-22)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1145/2535935
Cheng LXu WGong FLin YWong HHe L(2012)Statistical Timing and Power Optimization of Architecture and Device for FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/2209285.22092885:2(1-19)Online publication date: 1-Jun-2012
https://dl.acm.org/doi/10.1145/2209285.2209288
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A Flexible Power Model for FPGAs
1. Hardware
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Published In

cover image Guide Proceedings

FPL '02: Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications

September 2002

1181 pages

ISBN:3540441085

Publisher

Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 02 September 2002

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Cited By

Leong PAmano HAnderson JBertels KCardoso JDiessel OGogniat GHutton MLee JLuk WLysaght PPlatzner MPrasanna VRissa TSilvano CSo HWang Y(2017)The First 25 Years of the FPL ConferenceACM Transactions on Reconfigurable Technology and Systems10.1145/299646810:2(1-17)Online publication date: 22-Mar-2017
https://dl.acm.org/doi/10.1145/2996468
Leow YAkoglu ALysecky S(2013)An Analytical Model for Evaluating Static Power of Homogeneous FPGA ArchitecturesACM Transactions on Reconfigurable Technology and Systems10.1145/25359356:4(1-22)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1145/2535935
Cheng LXu WGong FLin YWong HHe L(2012)Statistical Timing and Power Optimization of Architecture and Device for FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/2209285.22092885:2(1-19)Online publication date: 1-Jun-2012
https://dl.acm.org/doi/10.1145/2209285.2209288
Rose JLuu JYu CDensmore OGoeders JSomerville AKent KJamieson PAnderson JCompton KHutchings B(2012)The VTR projectProceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays10.1145/2145694.2145708(77-86)Online publication date: 22-Feb-2012
https://dl.acm.org/doi/10.1145/2145694.2145708
Göhringer DObie JBraga AHübner MLlanos CBecker J(2011)Exploration of the power-performance tradeoff through parameterization of FPGA-based multiprocessor systemsInternational Journal of Reconfigurable Computing10.1155/2011/9859312011(1-17)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1155/2011/985931
Easwaran LAkoglu A(2011)Net-length-based routability-driven power-aware clusteringACM Transactions on Reconfigurable Technology and Systems10.1145/2068716.20687244:4(1-16)Online publication date: 28-Dec-2011
https://dl.acm.org/doi/10.1145/2068716.2068724
Jevtic RJovanovic BCarreras CAtienza DXie YAyala JStevens K(2011)Power estimation of dividers implemented in FPGAsProceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI10.1145/1973009.1973072(313-318)Online publication date: 2-May-2011
https://dl.acm.org/doi/10.1145/1973009.1973072
Zhu JWu DYan YYu XHe HPan LWawrzynek JCompton K(2011)A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only)Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1950413.1950475(281-281)Online publication date: 27-Feb-2011
https://dl.acm.org/doi/10.1145/1950413.1950475
Kumar DKumar PPattanaik MMartino JAraújo GOrailoglu AKlein F(2010)Performance analysis of dynamic threshold MOS (DTMOS) based 4-input multiplexer switch for low power and high speed FPGA designProceedings of the 23rd symposium on Integrated circuits and system design10.1145/1854153.1854156(2-7)Online publication date: 6-Sep-2010
https://dl.acm.org/doi/10.1145/1854153.1854156
Anderson JRavishankar CCheung PWawrzynek J(2010)FPGA power reduction by guarded evaluationProceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1723112.1723141(157-166)Online publication date: 21-Feb-2010
https://dl.acm.org/doi/10.1145/1723112.1723141
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