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A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs

Published: 02 September 2002 Publication History

Abstract

This paper presents the evaluation in power consumption of a clocking technique for pipelined designs. The technique shows a dynamic power consumption saving of around 30% over a conventional global clocking mechanism. The results were obtained from a series of experiments of a systolic circuit implemented in Virtex-II devices. The conversion from a global-clocked pipelined design to the proposed technique is straightforward, preserving the original datapath design. The savings can be used immediately either as a power reduction benefit or to increase the frequency of operation of a design for the same power consumption.

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  • (2005)A power-efficient processor core for reactive embedded applicationsProceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture10.1007/11572961_12(131-142)Online publication date: 24-Oct-2005
  1. A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs

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    cover image Guide Proceedings
    FPL '02: Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
    September 2002
    1181 pages

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    Springer-Verlag

    Berlin, Heidelberg

    Publication History

    Published: 02 September 2002

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    • (2005)A power-efficient processor core for reactive embedded applicationsProceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture10.1007/11572961_12(131-142)Online publication date: 24-Oct-2005

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