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Speeding Up Image Computation by Using RTL Information

Published: 01 November 2000 Publication History

Abstract

Image computation is the core operation for optimization and formal verification of sequential systems like controllers or protocols. State exploration techniques based on OBDDs use a partitioned representation of the transition relation to keep the OBDD-sizes manageable. This paper presents a new approach that significantly increases the quality of the partitioning of the transition relation of controllers given in the hardware description language Verilog. The heuristic has been successfully applied to reachability analysis and symbolic model checking of real life designs, resulting in a significant reduction both in CPU time and memory consumption.

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Cited By

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  • (2006)Decomposing image computation for symbolic reachability analysis using control flow informationProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233662(779-785)Online publication date: 5-Nov-2006
  • (2001)A new partitioning scheme for improvement of image computationProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370289(97-102)Online publication date: 30-Jan-2001

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Published In

cover image Guide Proceedings
FMCAD '00: Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
November 2000
537 pages
ISBN:3540412190

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Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 01 November 2000

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View all
  • (2006)Decomposing image computation for symbolic reachability analysis using control flow informationProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233662(779-785)Online publication date: 5-Nov-2006
  • (2001)A new partitioning scheme for improvement of image computationProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370289(97-102)Online publication date: 30-Jan-2001

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