Verification of Transaction-Level SystemC models using RTL Testbenches

System architects working on SoC design havetraditionally been hampered by the lack of a coherentemethodology for architecture evaluation and coverificationof hardware and software. SystemC 2.0facilitates the development of Transaction-Level Models(TLMs) which are models of the hardware systemcomponents at higher level of abstraction than RTL. Dueto lower modeling effort yet higher simulation speed,TLMs are useful for architectural exploration,algorithmic evaluation, hardware-software partitioningand software development. The problems posed by SOCdesign methodologies require development of models athigher abstraction also for the earlier developed IP's.The development time of a TLM IP is already low, so if wecan reduce the verification time by re-use of the earlierRTL test benches we can reduce the overall cost of suchan IP TLM. This paper focusses on the methodology touse the RTL testbenches for verification of a SystemCmodel of the same IP at a higher abstraction level(Transaction level), some tools available in the marketto support this testbench reuse and the implementationchallenges posed by the mentioned verificationtechnique.