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Verification of asynchronous interface circuits with bounded wire delays

Published: 08 November 1992 Publication History
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References

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M. C. Browne, E. M. Clarke, and D. L. Dill. Automatic Circuit Verification Using Temporal Logic: Two new examples. In Proceedings of Int'l Conference on Computer Design: VLSI in Computers, October 1985.
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R. Bryant. Graph-Based Algorithms for Boolean Function Manipulation. In IEEE Transactions on Computers, volume C-35, pages 677-691, August 1986.
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J. Burch. Delay Models for Verifying Speed Dependent Asynchronous Circuits. In Proceedings, Tau 92:1992 A CM Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March 1992.
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O. Coudert, C. Berthet, and J. C. Madre. Verification of Sequential Machines Using Boolean Functional Vectors. In IMEC-IFIP Int'i Workshop on Applied Formal Methods for Correct VLSI Design, pages 111-128, November 1989.
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S. Devadas, K. Keutzer, S. Malik, and A. Wang. Event Suppression: Improving the Efficiency of Timing Simulation for Synchronous Digital Circuits. In Proceedings of the Brown/MIT Advanced Research in VLSI and Parallel Systems, pages 195-209, March 1992.
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S. Devadas, K. Keutzer, S. Malik, and A. Wang. Verification of Asynchronous Circuits with Bounded Wire Delays. In Massachusetts Institute of Technology Technical Report, March 1992.
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S. Devadas, H-K. T. Ma, and A. R. Newton. On the Verification of Sequential Machines at Differing Levels of Abstraction. In IEEE Transactions on Computer-Aided Design, pages 713-722, June 1988. Correction in May 1989.
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D. L. Dill. Trace Theory for the Automatic Hierarchical Verification of Speed-Independent Circuits. MIT Press, 1987.
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D. L. Dill. Timing Assumptions and Verification of Finite-State Concurrent Systems. In Proceedings of the Workshop on Automatic Verification Methods for Finite State Systems, Volume 407 of Lecture Notes in Computer Science, June 1989.
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A. D. Friedman and P. R. Menon. Theory and Design of Switching Circuits. Computer Science Press, 1975.
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A. Ghosh, S. Devadas, and A. R. Newton. Verification of Interacting Sequential Circuits. In Proceedings of the 27th Design Automation Conference, pages 213-219, June 1990.
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N. Ishiura, Y. Deguchi, and S. Yajima. Coded Time-Symbolic Simulation using Shared Binary Decision Diagrams. In Proceedings of the 27th Design Automation Conference, pages 130-135, June 1990.
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N. Ishiura, M. Takahashi, and S. Yajima. Time- Symbolic Simulation for Accurate Timing Verification. In Proceedings of the 26~h Design Automation Conference, pages 497-502, June 1989.
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L. Lavagno, K. Keutzer, and A. Sangiovanni- Vincentelli. Algorithms for synthesis of hazardfree asynchronous circuits. In Proceedings of lhe Design Automation Conference, June 1991.
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S. H. Unger. Asynchronous Sequenlial Switching Circuits. Wiley Interscience, 1969.

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        cover image ACM Conferences
        ICCAD '92: Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
        November 1992
        637 pages
        ISBN:0897915402

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        IEEE Computer Society Press

        Washington, DC, United States

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        Published: 08 November 1992

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