Verification of asynchronous interface circuits with bounded wire delays
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Verification of asynchronous interface circuits with bounded wire delays
Special issue: asynchronous circuit design for VLSI signal processingWe address the problem of verifying that the gate-level implementation of an asynchronous circuit, with given or extracted bounds on wire and gate delays, is equivalent to a specification of the asynchronous circuit behavior described as a classical ...
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ATS '98: Proceedings of the 7th Asian Test SymposiumVerifying the correctness of asynchronous circuits is one of the most important task in asynchronous design. However, the absence of the global clock and the variation of gate delays in asynchronous circuits makes the verification a formidable task. In ...
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This paper considers the general problem of the synthesis of asynchronous combinational and sequential circuits based on the assumption that gate delays may be unbounded and that line delays are suitably constrained. Certain problems inherent to circuit ...
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