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State relaxation based subsequence removal for fast static compaction in sequential circuits

Authors:

M. S. Hsiao,

S. T. ChakradharAuthors Info & Claims

DATE '98: Proceedings of the conference on Design, automation and test in Europe

Pages 577 - 582

Published: 23 February 1998 Publication History

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Abstract

We extend the subsequence removal technique to provide significantly higher static compaction for sequential circuits. We show that state relaxation techniques can be used to identify more or larger cycles in a test set. State relaxation creates more opportunities for subsequence removal and hence, results in better compaction. Relaxation of a state is possible since not all memory elements in a finite state machine have to be specified for a state transition. The proposed technique has several advantages: (1) test sets that could not be compacted by existing subsequence removal techniques can now be compacted, (2) the size of cycles in a test set can be significantly increased by state relaxation and removal of the larger sized cycles leads to better compaction, (3) only two fault simulation passes are required as compared to trial and re-trial methods that require multiple fault simulation passes, and (4) significantly higher compaction is achieved in short execution times as compared to known subsequence removal methods. Experiments on ISCAS89 sequential benchmark circuits and several synthesized circuits show that the proposed technique consistently results in significantly higher compaction in short execution times.

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Cited By

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Pomeranz I(2015)FOLDACM Transactions on Design Automation of Electronic Systems10.1145/276445520:4(1-19)Online publication date: 28-Sep-2015
https://dl.acm.org/doi/10.1145/2764455
Pomeranz I(2015)A Generalized Definition of Unnecessary Test Vectors in Functional Test SequencesACM Transactions on Design Automation of Electronic Systems10.1145/269985320:2(1-13)Online publication date: 2-Mar-2015
https://dl.acm.org/doi/10.1145/2699853
Pomeranz IReddy S(2002)Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector OmissionIEEE Transactions on Computers10.1109/TC.2002.101770551:7(866-872)Online publication date: 1-Jul-2002
https://dl.acm.org/doi/10.1109/TC.2002.1017705
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State relaxation based subsequence removal for fast static compaction in sequential circuits

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Published In

DATE '98: Proceedings of the conference on Design, automation and test in Europe

February 1998

940 pages

ISBN:0818683597

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IEEE Computer Society

United States

Publication History

Published: 23 February 1998

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DATE98: Design, Automation & Test in Europe

February 23 - 26, 1998

Le Palais des Congrés de Paris, France

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all

Pomeranz I(2015)FOLDACM Transactions on Design Automation of Electronic Systems10.1145/276445520:4(1-19)Online publication date: 28-Sep-2015
https://dl.acm.org/doi/10.1145/2764455
Pomeranz I(2015)A Generalized Definition of Unnecessary Test Vectors in Functional Test SequencesACM Transactions on Design Automation of Electronic Systems10.1145/269985320:2(1-13)Online publication date: 2-Mar-2015
https://dl.acm.org/doi/10.1145/2699853
Pomeranz IReddy S(2002)Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector OmissionIEEE Transactions on Computers10.1109/TC.2002.101770551:7(866-872)Online publication date: 1-Jul-2002
https://dl.acm.org/doi/10.1109/TC.2002.1017705
Pomeranz IReddy S(2001)Sequence reordering to improve the levels of compaction achievable by static compaction proceduresProceedings of the conference on Design, automation and test in Europe10.5555/367072.367158(214-218)Online publication date: 13-Mar-2001
https://dl.acm.org/doi/10.5555/367072.367158
Pomeranz IReddy S(2000)Procedures for Static Compaction of Test Sequences for Synchronous Sequential CircuitsIEEE Transactions on Computers10.1109/12.86221949:6(596-607)Online publication date: 1-Jun-2000
https://dl.acm.org/doi/10.1109/12.862219
Hsiao MChakradhar S(2000)Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential CircuitsJournal of Electronic Testing: Theory and Applications10.1023/A:100831390193816:4(329-338)Online publication date: 1-Aug-2000
https://dl.acm.org/doi/10.1023/A%3A1008313901938
Pomeranz IReddy SWhite JSentovich E(1999)An approach for improving the levels of compaction achieved by vector omissionProceedings of the 1999 IEEE/ACM international conference on Computer-aided design10.5555/339492.340060(463-466)Online publication date: 7-Nov-1999
https://dl.acm.org/doi/10.5555/339492.340060
Rudnick EPatel J(1999)Efficient Techniques for Dynamic Test Sequence CompactionIEEE Transactions on Computers10.1109/12.75499848:3(323-330)Online publication date: 1-Mar-1999
https://dl.acm.org/doi/10.1109/12.754998
Bommu SChakradhar SDoreswamy KYasuura H(1998)Static compaction using overlapped restoration and segment pruningProceedings of the 1998 IEEE/ACM international conference on Computer-aided design10.1145/288548.288592(140-146)Online publication date: 1-Nov-1998
https://dl.acm.org/doi/10.1145/288548.288592

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Dynamic test compaction for synchronous sequential circuits using static compaction techniques