Article

Partitioning circuits for inproved testability

Authors:

Sandeep N. Bhatt,

Fan R. K. Chung,

Arnold L. RosenbergAuthors Info & Claims

Proceedings of the fourth MIT conference on Advanced research in VLSI

Pages 91 - 106

Published: 01 June 1986 Publication History

Abstract

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Jone WRau JChang SWu Y(1998)A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuitsProceedings of the 1998 IEEE International Test Conference10.5555/648020.745632(322-330)Online publication date: 18-Oct-1998
https://dl.acm.org/doi/10.5555/648020.745632
Srinivasan RGupta SBreuer MDunlop A(1993)An efficient partitioning strategy for pseudo-exhaustive testingProceedings of the 30th international Design Automation Conference10.1145/157485.164880(242-248)Online publication date: 1-Jul-1993
https://dl.acm.org/doi/10.1145/157485.164880
Hellebrand SWunderlich HAdshead GJess J(1990)Tools and devices supporting the pseudo-exhaustive testProceedings of the conference on European design automation10.5555/949970.949974(13-17)Online publication date: 12-Mar-1990
https://dl.acm.org/doi/10.5555/949970.949974
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Index Terms

Partitioning circuits for inproved testability
1. Hardware
  1. Hardware test
    1. Design for testability
  2. Very large scale integration design
2. Theory of computation
  1. Formal languages and automata theory

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The importance of redundant technologies for improving dependability and delay fault testability are growing. This paper presents properties of a class of redundant technologies, namely two-rail logic, and discusses testability of path delay faults ...
Partitioning circuits for improved testability
Abstract
Exhaustive self-testing of combinational circuitry within the framework of the level-sensitive scan design (LSSD) discipline requires that every output node depend on a small number of input nodes. We present here efficient algorithms that take an ...
Testability of 2-Level AND/EXOR Circuits

It is often stated that AND/EXOR circuits are much easier to test than AND/OR circuits. This statement, however, only holds true for circuits derived from restricted classes of AND/EXOR expressions, like positive polarity Reed-Muller and fixed polarity ...

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Published In

Proceedings of the fourth MIT conference on Advanced research in VLSI

June 1986

318 pages

ISBN:0262121131

Editor:
Charles E. Leiserson
Massachusetts Institute of Technology

Publisher

MIT Press

Cambridge, MA, United States

Publication History

Published: 01 June 1986

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Cited By

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Jone WRau JChang SWu Y(1998)A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuitsProceedings of the 1998 IEEE International Test Conference10.5555/648020.745632(322-330)Online publication date: 18-Oct-1998
https://dl.acm.org/doi/10.5555/648020.745632
Srinivasan RGupta SBreuer MDunlop A(1993)An efficient partitioning strategy for pseudo-exhaustive testingProceedings of the 30th international Design Automation Conference10.1145/157485.164880(242-248)Online publication date: 1-Jul-1993
https://dl.acm.org/doi/10.1145/157485.164880
Hellebrand SWunderlich HAdshead GJess J(1990)Tools and devices supporting the pseudo-exhaustive testProceedings of the conference on European design automation10.5555/949970.949974(13-17)Online publication date: 12-Mar-1990
https://dl.acm.org/doi/10.5555/949970.949974
Wu CCappello P(1990)Easily Testable Iterative Logic ArraysIEEE Transactions on Computers10.1109/12.5357739:5(640-652)Online publication date: 1-May-1990
https://dl.acm.org/doi/10.1109/12.53577
Jone WPapachristou CThomas D(1989)A coordinated approach to partitioning and test pattern generation for pseudoexhaustive testingProceedings of the 26th ACM/IEEE Design Automation Conference10.1145/74382.74470(525-534)Online publication date: 1-Jun-1989
https://dl.acm.org/doi/10.1145/74382.74470

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Recommendations

Delay Fault Testability on Two-Rail Logic Circuits

Partitioning circuits for improved testability

Testability of 2-Level AND/EXOR Circuits

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