[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
10.5555/266800.266827acmconferencesArticle/Chapter ViewAbstractPublication PagesmicroConference Proceedingsconference-collections
Article
Free access

Highly accurate data value prediction using hybrid predictors

Published: 01 December 1997 Publication History

Abstract

Data dependences (data flow constraints) present a major hurdle to the amount of instruction-level parallelism that can be exploited from a program. Recent work has suggested that the limits imposed by data dependences can be overcome to some extent with the use of data value prediction. That is, when an instruction is fetched, its result can be predicted so that subsequent instructions that depend on the result can use this predicted value. When the correct result becomes available, all instructions that are data dependent on that prediction can be validated. This paper investigates a variety of techniques to carry out highly accurate data value predictions. The first technique investigates the potential of monitoring the strides by which the results produced by different instances of an instruction change. The second technique investigates the potential of pattern-based two-level prediction schemes. Simulation results of these two schemes show improvements over the existing method of predicting the last outcome. In particular, some benchmarks show improvement with the stride-based predictor and others show improvement with the pattern-based predictor. To do uniformly well across benchmarks, we combine these two predictors to form a hybrid predictor. Simulation analysis of the hybrid predictor shows its overall prediction accuracy to be better than that of the component predictors across all benchmarks.

References

[1]
T. M. Austin and G. S. Sohi, "Dynamic Dependency Analysis of Ordinary Programs," Proceedings of 19th Annual International Symposium on Computer Architecture, pp. 342-351, 1992.
[2]
M. Butler, T. Yeh, Y. Patt, M. Alsup, H. Scales, and M. Shebanow, "Single Instruction Stream Parallelism Is Greater than Two," Proceedings of 181h Annual International Symposium on Computer Architecture, pp. 276-286, 1991.
[3]
T. Chen and J-L. Baer, "Effective Hardware- Based Data Prefetching for High-Performance Processors," IEEE Transactions on Computers, vol. 44, no. 5, pp. 609-623, May 1995.
[4]
F. Dahlgren and P. Stenstrom, "Evaluation of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors," IEEE Transactions on Parallel and Dislributed Systems, vol. 7, no. 4, pp. 385-398, April 1996.
[5]
S. Dutta and M. Franklin, "Control Flow Prediction with Tree-like Subgraphs for Superscalar Processors," Proc. 28th International Symposium on Microarchitecture (MICRO-28), pp. 258-263, 1995.
[6]
W. W. Hwu et al, "Compiling for ILP Processors,'' Proceedings of the IEEE, Vol. 83, No. 12, December 1995.
[7]
M. S. Lam and R. P. Wilson, "Limits of Control Flow on Parallelism," Proceedings of 19th Annual International Symposium on Computer Architecture, pp. 46-57, 1992.
[8]
M. H. Lipasti, C. B. Wilkerson, and J. P. Shen, "Value Locality and Load Value Prediction," Proceedings of VIIth International Uonference on A rchiiectural Support for Programming Languages and Operating Systems (ASPLO$-VII), 1996.
[9]
M. H. Lipasti and J. P. Shen, "Exceeding the Datafiow Limit via Value Prediction," Proceedings of 29th International Symposium on Microarchiteciure (MICRO-29), pp. 226-237 1996.
[10]
R. K. Montoye, E. Hokenek, and S. L. Runyon, "Design of the IBM RISC Ssytem/6000 Floating- Point Execution Unit," IBM Journal of Research and Development, Vol. 34, No. 1, pp. 59-70, January 1990'.
[11]
R. Nair, "Dynamic Path-Based Branch Correlation,'' Proc. ~Sth Annual International Symposium on Microarchitecture (MICRO-28), 1995.
[12]
S-T. Pan, K. So, and J. T. Rahmeh, "Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation," Proceedings of the Fifth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLO$-V), pp. 76-84, 1992.
[13]
J. E. Smith and G. S. Sohi, "The Microarchitecture of Superscalar Processors," Proceedings of the IEEE, Vol. 83, No. 12, pp. 1609-1624, December 1995.
[14]
A. Sodani and G. S. Sohi, "Dynamic Instruction Reuse," Proceedings of ~dth Annual international Symposium on Computer Architecture, 1997.
[15]
T-Y Yeh and Y. N. Patt, "Alternative Implementations of Two-Level Adaptive Branch Prediction,'' Proceedings of the 19th Annual b~ternational Symposium on Computer A rchitccturc~ pp. 124-134, 1992.

Cited By

View all
  • (2022)OnSRAM: Efficient Inter-Node On-Chip Scratchpad Management in Deep Learning AcceleratorsACM Transactions on Embedded Computing Systems10.1145/353090921:6(1-29)Online publication date: 18-Oct-2022
  • (2021)Early Address PredictionACM Transactions on Architecture and Code Optimization10.1145/345888318:3(1-22)Online publication date: 8-Jun-2021
  • (2020)Relaxed Reorder Buffer Commit with Batch Context SwitchProceedings of the International Conference on Computing Advancements10.1145/3377049.3377088(1-5)Online publication date: 10-Jan-2020
  • Show More Cited By

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences
MICRO 30: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
December 1997
369 pages
ISBN:0818679778

Sponsors

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 December 1997

Check for updates

Author Tags

  1. Data speculation
  2. Instruction-level parallel (ILP) processing Speculative execution
  3. Stride-based prediction
  4. Two-level prediction

Qualifiers

  • Article

Conference

MICRO97
Sponsor:
MICRO97: 30th Annual International Symposium on Microarchitecture
December 1 - 3, 1997
North Carolina, Research Triangle Park, USA

Acceptance Rates

MICRO 30 Paper Acceptance Rate 35 of 103 submissions, 34%;
Overall Acceptance Rate 484 of 2,242 submissions, 22%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)42
  • Downloads (Last 6 weeks)5
Reflects downloads up to 10 Dec 2024

Other Metrics

Citations

Cited By

View all
  • (2022)OnSRAM: Efficient Inter-Node On-Chip Scratchpad Management in Deep Learning AcceleratorsACM Transactions on Embedded Computing Systems10.1145/353090921:6(1-29)Online publication date: 18-Oct-2022
  • (2021)Early Address PredictionACM Transactions on Architecture and Code Optimization10.1145/345888318:3(1-22)Online publication date: 8-Jun-2021
  • (2020)Relaxed Reorder Buffer Commit with Batch Context SwitchProceedings of the International Conference on Computing Advancements10.1145/3377049.3377088(1-5)Online publication date: 10-Jan-2020
  • (2018)AVPPACM Transactions on Architecture and Code Optimization10.1145/323956715:4(1-30)Online publication date: 7-Dec-2018
  • (2018)Approximate CommunicationACM Computing Surveys10.1145/314581251:1(1-32)Online publication date: 10-Jan-2018
  • (2016)Register sharing for equality predictionThe 49th Annual IEEE/ACM International Symposium on Microarchitecture10.5555/3195638.3195643(1-12)Online publication date: 15-Oct-2016
  • (2016)Resource boxingProceedings of the 9th International Conference on Utility and Cloud Computing10.1145/2996890.2996897(138-147)Online publication date: 6-Dec-2016
  • (2016)EOLEACM Transactions on Computer Systems10.1145/287063234:2(1-33)Online publication date: 21-Apr-2016
  • (2014)EOLEProceeding of the 41st annual international symposium on Computer architecuture10.5555/2665671.2665742(481-492)Online publication date: 14-Jun-2014
  • (2014)EOLEACM SIGARCH Computer Architecture News10.1145/2678373.266574242:3(481-492)Online publication date: 14-Jun-2014
  • Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media