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Networks on chips for high-end consumer-electronics TV system architectures

Published: 06 March 2006 Publication History

Abstract

Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SOCs are application-specific standard products (ASSPs) with limited programmability. We describe why TV SOCs must become more flexible, and why companion chips together with networks on chips (NOC) are a crucial enabling technology. In particular, networks that span multiple chips will become important in the near future.We demonstrate our ideas by extending a commercially-available SOC for picture improvement in high-end TVs with the Æthereal NOC. Our first unoptimised results indicate that replacing the original interconnect (consisting of dedicated links and multiplexers for bypasses) by programmable NOC increases the SOC area by 4% and its power dissipation by 12%. The new, flexible SOC allows new tasks to be spliced in at any point in the task graph. Both analytical performance verification and system simulations at RTL VHDL show that the extended SOC meets its functional requirements. Using the Æthereal design flow the extended architecture was designed, implemented, and verified in 12 person months.To the best of our knowledge, this is the first application of a NOC to a commercial SOC. The quantitive results indicate that even retrofitting a NOC to an existing architecture is beneficial at acceptable cost.

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Cited By

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  • (2009)An on-chip interconnect and protocol stack for multiple communication paradigms and programming modelsProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629450(99-108)Online publication date: 11-Oct-2009
  • (2009)A methodology for application-specific NoC architecture generation in a dynamic task structure environmentProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531580(149-152)Online publication date: 10-May-2009
  • (2008)Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration InterconnectsProceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip10.5555/1397757.1397986(45-54)Online publication date: 7-Apr-2008
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Information & Contributors

Information

Published In

cover image Guide Proceedings
DATE '06: Proceedings of the conference on Design, automation and test in Europe: Designers' forum
March 2006
262 pages
ISBN:3981080106

Sponsors

  • EDAA: European Design Automation Association
  • The EDA Consortium
  • IEEE-CS\DATC: The IEEE Computer Society

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European Design and Automation Association

Leuven, Belgium

Publication History

Published: 06 March 2006

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  • Article

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DATE '06 Paper Acceptance Rate 45 of 45 submissions, 100%;
Overall Acceptance Rate 518 of 1,794 submissions, 29%

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View all
  • (2009)An on-chip interconnect and protocol stack for multiple communication paradigms and programming modelsProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629450(99-108)Online publication date: 11-Oct-2009
  • (2009)A methodology for application-specific NoC architecture generation in a dynamic task structure environmentProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531580(149-152)Online publication date: 10-May-2009
  • (2008)Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration InterconnectsProceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip10.5555/1397757.1397986(45-54)Online publication date: 7-Apr-2008
  • (2007)PredatorProceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1289816.1289877(251-256)Online publication date: 30-Sep-2007
  • (2007)Efficient space-time noc path allocation based on mutual exclusion and pre-reservationProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228892(457-460)Online publication date: 11-Mar-2007
  • (2007)Transaction-Based Communication-Centric DebugProceedings of the First International Symposium on Networks-on-Chip10.1109/NOCS.2007.46(95-106)Online publication date: 7-May-2007
  • (2006)Layout aware design of mesh based NoC architecturesProceedings of the 4th international conference on Hardware/software codesign and system synthesis10.1145/1176254.1176288(136-141)Online publication date: 22-Oct-2006

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