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The Design of a Microsupercomputer

Published: 01 January 1991 Publication History

Abstract

A description is given of work to develop a prototype microcomputer that will realize the best of both the supercomputer and the microprocessor traditions. It does so by using GaAs MESFET enhancement/depletion direct-coupled FET logic, a high-speed technology that has good integration density, and state-of-the-art packaging technology to prevent chip crossings from dominating the overall speed of the system. The focus of the research reported is the relationship between hardware implementations and emerging technologies. The MIPS Computer Systems instruction set was implemented to bound the architectural options and to eliminate the need to develop compilers and operating systems. Efforts are concentrated on developing the processor and cache. The resulting system will be a general-purpose computer that runs a conventional Unix environment and supports standard programming languages and networking protocols. The machine will significantly accelerate execution of the existing large base of application software.

References

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1. J.L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann, San Mateo, Calif., 1990.
[2]
2. H. Vlahos and V. Milutinovic, "GaAs Microprocessors and Digital Systems," IEEE Micro, Vol. 8, No. 1, 1988, pp. 28-56.
[3]
3. G. Kane, MIPS RISC Architecture, Prentice Hall, Englewood Cliffs, N.J., 1988.
[4]
4. J.A. Dykstra, High-Speed Microprocessor Design with Gallium Arsenide Very Large Scale Integrated Digital Circuits, PhD dissertation, Univ. of Michigan, 1990.
[5]
5. H.B. Bakoglu, Circuits, Interconnects, and Packaging for VLSI, Addison-Wesley, Reading, Mass., 1990.
[6]
6. K.A. Sakallah, T.N. Mudge, and O.A. Olukotun, "checkTc and minTc: Timing Verification and Optimal Clocking of Synchronous Digital Circuits," Proc. ICCAD 90, Int'l Conf. on Computer-Aided Design, IEEE Computer Soc. Press, Los Alamitos, Calif., Order No. 2055, pp. 552-555.
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7. R.H. Voelker and R.J. Lomax, "A Finite-Difference Transmission Line Matrix Method Incorporating a Nonlinear Device Model," IEEE Trans. Microwave Theory and Techniques, Vol. 38, No. 3, Mar. 1990, pp. 302-312.
[8]
8. Y.C. Lee et al., "Internal Thermal Resistance of a Multi-Chip Packaging Design for VLSI Based Systems," IEEE Trans. Components, Hybrids, and Manufacturing Technology , Vol. 12, No. 2, June 1989, pp. 163- 169.
[9]
9. N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, Reading, Mass., 1985.
[10]
10. J.R. Goodman, "Coherency for Multiprocessor Virtual Address Caches," Proc. ASPLOS, Second Int'l Conf. Architectural Support for Programming Languages and Operating Systems, Oct. 1987, pp. 72-81.
[11]
11. RISCompiler Languages Programmer's Guide, MIPS Computer Systems, Inc., Santa Clara, Calif., Dec. 1988.
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12. A. Agarwal, Analysis of Cache Performance for Operating Systems and Multiprogramming , Kluwer Academic Publishers, Boston, Mass., 1988.

Cited By

View all
  • (1993)Efficient simulation of caches under optimal replacement with applications to miss characterizationACM SIGMETRICS Performance Evaluation Review10.1145/166962.16697421:1(24-35)Online publication date: 1-Jun-1993
  • (1993)Efficient simulation of caches under optimal replacement with applications to miss characterizationProceedings of the 1993 ACM SIGMETRICS conference on Measurement and modeling of computer systems10.1145/166955.166974(24-35)Online publication date: 1-Jun-1993
  • (1992)Delay macromodels for the timing analysis of GaAs DCFLProceedings of the conference on European design automation10.5555/159754.161744(142-145)Online publication date: 1-Nov-1992
  • Show More Cited By

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  1. The Design of a Microsupercomputer

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                          Reviews

                          Donald Quentin Marcus Fay

                          Detailed design concepts for a fast MIPS-compatible microprocessor with a two-level cache on a multichip module are described. Some components of the design have been fully implemented in the Mesfet technology developed by Vitesse Corporation. Simulations are described in some detail; these were carried out on VSPICE (a proprietary version of SPICE modified by Vitesse Corporation for its E/D Mesfet technology). The use of GaAs Mesfet E/D DCFL allows for a design clock rate of 250 MHz. The processor design has been kept simple, straightforward, and traditional. Any logical complexity appears in the two-level cache, which is needed to match the projected processor speed. A particular problem is imposed by the MIPS architecture, in which two different virtual addresses might map to the same physical memory address. The paper addresses two issues of particular interest for GaAs design. First, packaging is done in multi-chip modules (MCM) in order to avoid package-to-package communication delay penalties. Several MCM-related problems have been solved by cooling studies, transmission-line characterizations, and the design of drivers for 50–70 ohm characteristic impedance lines. Second, the current lack of CAD tools for GaAs design has been overcome by adapting existing silicon-oriented tools (such as customizing the layout generator for the four-metal-layer Vitesse GaAs process) and developing new tools such as a finite difference transmission-line matrix simulator, a timing analyzer, some optimization tools, and a simulator of cache memories. Implementation is not complete, but the reported simulation results look promising. The design is of a fast single microprocessor with single memory. The authors do not consider the connections to other processors that would be needed if this component were to form part of the design of a multiprocessor supercomputer. The paper clearly reports some of the technical results of collaborative research and development by a university and an industrial corporation. The references are useful.

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                          Information & Contributors

                          Information

                          Published In

                          cover image Computer
                          Computer  Volume 24, Issue 1
                          Special issue on experimental research in computer architecture
                          January 1991
                          102 pages
                          ISSN:0018-9162
                          Issue’s Table of Contents

                          Publisher

                          IEEE Computer Society Press

                          Washington, DC, United States

                          Publication History

                          Published: 01 January 1991

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                          Cited By

                          View all
                          • (1993)Efficient simulation of caches under optimal replacement with applications to miss characterizationACM SIGMETRICS Performance Evaluation Review10.1145/166962.16697421:1(24-35)Online publication date: 1-Jun-1993
                          • (1993)Efficient simulation of caches under optimal replacement with applications to miss characterizationProceedings of the 1993 ACM SIGMETRICS conference on Measurement and modeling of computer systems10.1145/166955.166974(24-35)Online publication date: 1-Jun-1993
                          • (1992)Delay macromodels for the timing analysis of GaAs DCFLProceedings of the conference on European design automation10.5555/159754.161744(142-145)Online publication date: 1-Nov-1992
                          • (1992)Performance optimization of pipelined primary cacheACM SIGARCH Computer Architecture News10.1145/146628.13972620:2(181-190)Online publication date: 1-Apr-1992
                          • (1992)Performance optimization of pipelined primary cacheProceedings of the 19th annual international symposium on Computer architecture10.1145/139669.139726(181-190)Online publication date: 19-May-1992
                          • (1991)Delayed consistency and its effects on the miss rate of parallel programsProceedings of the 1991 ACM/IEEE conference on Supercomputing10.1145/125826.125941(197-206)Online publication date: 1-Aug-1991
                          • (1991)Implementing a cache for a high-performance GaAs microprocessorACM SIGARCH Computer Architecture News10.1145/115953.11596719:3(138-147)Online publication date: 1-Apr-1991
                          • (1991)Implementing a cache for a high-performance GaAs microprocessorProceedings of the 18th annual international symposium on Computer architecture10.1145/115952.115967(138-147)Online publication date: 1-Apr-1991

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