Parallel verilog simulation: architecture and circuit partition

As a consequence of Moore’s law, the size of integrated circuits has grown extensively, resulting in simulation becoming the major bottleneck in the circuit design process. Consequently, parallel simulation has emerged as an approach which can be both ...

We describe, in this paper, a multiway partitioning algorithm for parallel gate level Verilog simulation. The algorithm is an extension of a multi-level algorithm which only creates two partitions. Like its predecessor, it takes advantage of the design ...

An implementation of a conservative parallel simulator with deadlock avoidance is presented. Its performance when working with a realistic model of a message routing network is evaluated and contrasted against a sequential simulator. Different factors ...