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Parallel algorithms for VLSI computer-aided designJanuary 1994
- Author:
- Prithviraj Banerjee
Abstract
No abstract available.
Cited By
- Chasapis D, Casas M, Moretó M, Vidal R, Ayguadé E, Labarta J and Valero M (2015). PARSECSs, ACM Transactions on Architecture and Code Optimization, 12:4, (1-22), Online publication date: 7-Jan-2016.
- Sawada H, Kuga M, Amagasaki M, Iida M and Sueyoshi T (2011). Parallelization of the channel width search for FPGA routing, ACM SIGARCH Computer Architecture News, 39:4, (82-85), Online publication date: 19-Dec-2011.
- Meraji S, Zhang W and Tropper C (2010). On the scalability and dynamic load-balancing of optimistic gate level simulation, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29:9, (1368-1380), Online publication date: 1-Sep-2010.
- Gulati K and Khatri S (2010). Fault Table Computation on GPUs, Journal of Electronic Testing: Theory and Applications, 26:2, (195-209), Online publication date: 1-Apr-2010.
- Meraji S, Zhang W and Tropper C On the scalability and dynamic load balancing of parallel Verilog simulations Winter Simulation Conference, (1366-1374)
- Bienia C, Kumar S, Singh J and Li K The PARSEC benchmark suite Proceedings of the 17th international conference on Parallel architectures and compilation techniques, (72-81)
- Gulati K and Khatri S Towards acceleration of fault simulation using graphics processing units Proceedings of the 45th annual Design Automation Conference, (822-827)
- Minhas M and Sait S A parallel tabu search algorithm for optimizing multiobjective VLSI placement Proceedings of the 2005 international conference on Computational Science and Its Applications - Volume Part IV, (587-595)
- Baños R, Gil C, Ortega J and Montoya F (2019). A Parallel Multilevel Metaheuristic for Graph Partitioning, Journal of Heuristics, 10:3, (315-336), Online publication date: 1-May-2004.
- Reed D, Levitan S, Boles J, Martinez J and Chiarulli D An Application of Parallel Discrete Event Simulation Algorithms to Mixed Domain System Simulation Proceedings of the conference on Design, automation and test in Europe - Volume 2
- Li T, guo Y, Li S, Ao F and Li G Parallel verilog simulation Proceedings of the 2004 Asia and South Pacific Design Automation Conference, (644-646)
- Li L, Huang H and Tropper C DVS Proceedings of the seventeenth workshop on Parallel and distributed simulation
- Baños R, Gil C, Ortega J and Montoya F Multilevel heuristic algorithm for graph partitioning Proceedings of the 2003 international conference on Applications of evolutionary computing, (143-153)
- Wrighton M and DeHon A Hardware-assisted simulated annealing with application for fast FPGA placement Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, (33-42)
- Chattopadhyay S and Choudhary N Genetic Algorithm based Approach for Low Power Combinational Circuit Testing Proceedings of the 16th International Conference on VLSI Design
- Gil C, Ortega J, Montoya M and Baños R (2019). A Mixed Heuristic for Circuit Partitioning, Computational Optimization and Applications, 23:3, (321-340), Online publication date: 1-Dec-2002.
- Kim V, Banerjee P and De K Fine-Grained Parallel VLSI Synthesis for Commercial CAD on a Network of Workstations Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing
- Prabhakaran P and Banerjee P (1999). Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs, IEEE Transactions on Computers, 48:7, (762-768), Online publication date: 1-Jul-1999.
- Frey P, Nellayappan K, Sahnmugasundaram V, Mayiladuthurai R, Chandrashekar C and Carter H SEAMS Proceedings of the 30th conference on Winter simulation, (539-546)
- Kim V and Banerjee P Parallel algorithms for power estimation Proceedings of the 35th annual Design Automation Conference, (672-677)
- Xing Z and Banerjee P A parallel algorithm for zero skew clock tree routing Proceedings of the 1998 international symposium on Physical design, (118-123)
- Krauss P, Ganz A and Antreich K (2019). Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits, Journal of Electronic Testing: Theory and Applications, 11:3, (227-245), Online publication date: 1-Dec-1997.
- Holm J, Chandy J, Parkes S, Roy S, Krishnaswamy V, Hasteer G and Banerjee P Performance evaluation of message-driven parallel VLSI CAD applications on general purpose multiprocessors Proceedings of the 11th international conference on Supercomputing, (172-179)
- Krishnaswamy D, Banerjee P, Rudnick E and Patel J (1997). Asynchronous parallel algorithms for test set partitioned fault simulation, ACM SIGSIM Simulation Digest, 27:1, (30-37), Online publication date: 1-Jul-1997.
- Krishnaswamy D, Banerjee P, Rudnick E and Patel J Asynchronous parallel algorithms for test set partitioned fault simulation Proceedings of the eleventh workshop on Parallel and distributed simulation, (30-37)
- Amin M and Vinnakota B (2019). Workload Distribution in Fault Simulation, Journal of Electronic Testing: Theory and Applications, 10:3, (277-282), Online publication date: 1-Jun-1997.
- Krishnaswamy D, Rudnick E, Patel J and Banerjee P SPITFIRE Proceedings of the 15th IEEE VLSI Test Symposium
- Xing Z, Chandy J and Banerjee P Parallel Global Routing Algorithms for Standard Cells Proceedings of the 11th International Symposium on Parallel Processing
- Rudnick E and Patel J Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
- Krishnaswamy D, Hsiao M, Saxena V, Rudnick E, Patel J and Banerjee P Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
- Hasteer G and Banerjee P Simulated Annealing Based Parallel State Assignment of Finite State Machines Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
- Scherber F, Barke E and Meier W PALACE Proceedings of the 1996 European conference on Design and Test
Index Terms
- Parallel algorithms for VLSI computer-aided design
Reviews
Linda Pagli
A long research project conducted by Banerjee, a keen expert in the field, and his graduate students at the University of Illinois has resulted in this book. The motivations for parallel VLSI design are largely projected in the future (the book thus has a strong research flavor); still, the availability of large parallel processors makes the proposed approach relevant in the present also. Parallel computing allows design routines to run much faster, and large memory requirements to be met more easily. These features are particularly important in a field where many problems are large and NP-hard, so that simple and easy parallelizable heuristics are readily adopted, instead of searching for improbable “smart” algorithms. The book starts with a review of parallel architectures and their programming. Then, all the phases of the VLSI design process are studied, and the parallel strategies for their treatment are deeply analyzed. These phases include placement and floor planning, routing , layout verification, circuit and logic simulation, logic synthesis, and verification. The book is a useful tool for professionals and a good basic reference for researchers.
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