Cited By
View all- Li Tguo YLi SAo FLi GImai M(2004)Parallel verilog simulationProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015265(644-646)Online publication date: 27-Jan-2004
In this paper we present a parallel formulation of a multilevel k-way graph partitioning algorithm. The multilevel k-way partitioning algorithm reduces the size of the graph by collapsing vertices and edges (coarsening phase), finds a k-way partition of ...
Multi-delay logic simulation may perform many logic simulations for each gate in the circuit during the simulation of a single input vector. Conventional event driven simulation will perform each of these gate-simulations as a separate operation, ...
In this paper we present a parallel formulation of a multilevel k-way graph partitioning algorithm. A key feature of this parallel formulation is that it is able to achieve a high degree of concurrency while maintaining the high quality of the ...
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