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A retargetable register allocation framework for embedded processors

Authors:

Jean-Marc Daveau,

Thierry Lepley,

Miguel SantanaAuthors Info & Claims

LCTES '04: Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems

Pages 202 - 210

https://doi.org/10.1145/997163.997192

Published: 11 June 2004 Publication History

Abstract

This paper describes the FlexCC2 register allocation framework. FlexCC2 is an optimizing retargetable C compiler for embedded processors, and in particular for DSP processors. Embedded processors often contain features such as irregular and constrained register sets that complicate register allocation, making traditional methods inefficient. In this paper, we present a register allocation framework specifically tailored for embedded processor specificities. This framework has been integrated in the FlexCC2 production compiler and is used by FlexCC2 customers.

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Cited By

Lee YChen C(2018)An Efficient Code Generation Algorithm for Non-orthogonal DSP ArchitectureJournal of VLSI Signal Processing Systems10.1007/s11265-007-0053-x47:3(281-296)Online publication date: 26-Dec-2018
https://dl.acm.org/doi/10.1007/s11265-007-0053-x
Lintzmayer CMulati MSilva A(2012)Register Allocation by Evolutionary AlgorithmProceedings of the 2012 31st International Conference of the Chilean Computer Science Society10.1109/SCCC.2012.31(207-215)Online publication date: 12-Nov-2012
https://dl.acm.org/doi/10.1109/SCCC.2012.31
Xavier TOliveira GLima ESilva A(2012)A Detailed Analysis of the LLVM's Register AllocatorsProceedings of the 2012 31st International Conference of the Chilean Computer Science Society10.1109/SCCC.2012.29(190-198)Online publication date: 12-Nov-2012
https://dl.acm.org/doi/10.1109/SCCC.2012.29
Show More Cited By

Index Terms

A retargetable register allocation framework for embedded processors
1. Software and its engineering
  1. Software notations and tools
    1. Compilers
      1. Retargetable compilers

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A retargetable register allocation framework for embedded processors
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Information

Published In

cover image ACM Conferences

LCTES '04: Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems

June 2004

276 pages

ISBN:1581138067

DOI:10.1145/997163

General Chair:
David Whalley
Florida State University
,
Program Chair:
Ron Cytron
Washington University

ACM SIGPLAN Notices Volume 39, Issue 7
LCTES '04
July 2004
265 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/998300
Issue’s Table of Contents

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 11 June 2004

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LCTES04

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LCTES04: Languages, Compilers, and Tools for Embedded Systems 2004

June 11 - 13, 2004

DC, Washington, USA

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Overall Acceptance Rate 116 of 438 submissions, 26%

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Cited By

Lee YChen C(2018)An Efficient Code Generation Algorithm for Non-orthogonal DSP ArchitectureJournal of VLSI Signal Processing Systems10.1007/s11265-007-0053-x47:3(281-296)Online publication date: 26-Dec-2018
https://dl.acm.org/doi/10.1007/s11265-007-0053-x
Lintzmayer CMulati MSilva A(2012)Register Allocation by Evolutionary AlgorithmProceedings of the 2012 31st International Conference of the Chilean Computer Science Society10.1109/SCCC.2012.31(207-215)Online publication date: 12-Nov-2012
https://dl.acm.org/doi/10.1109/SCCC.2012.31
Xavier TOliveira GLima ESilva A(2012)A Detailed Analysis of the LLVM's Register AllocatorsProceedings of the 2012 31st International Conference of the Chilean Computer Science Society10.1109/SCCC.2012.29(190-198)Online publication date: 12-Nov-2012
https://dl.acm.org/doi/10.1109/SCCC.2012.29
Lintzmayer CMulati MSilva A(2011)Register Allocation with Graph Coloring by Ant Colony OptimizationProceedings of the 2011 30th International Conference of the Chilean Computer Science Society10.1109/SCCC.2011.32(247-255)Online publication date: 9-Nov-2011
https://dl.acm.org/doi/10.1109/SCCC.2011.32
Ahn MPaek Y(2009)Register coalescing techniques for heterogeneous register architecture with copy siftingACM Transactions on Embedded Computing Systems (TECS)10.1145/1457255.14572638:2(1-37)Online publication date: 9-Feb-2009
https://dl.acm.org/doi/10.1145/1457255.1457263
Venturini HRiss FFernandez JSantana MFalk H(2008)A fully-non-transparent approach to the code location problemProceedings of the 11th international workshop on Software & compilers for embedded systems10.1145/1361096.1361108(61-68)Online publication date: 13-Mar-2008
https://dl.acm.org/doi/10.1145/1361096.1361108
Ahn MLee JPaek Y(2007)Optimistic coalescing for heterogeneous register architecturesACM SIGPLAN Notices10.1145/1273444.125478142:7(93-102)Online publication date: 13-Jun-2007
https://dl.acm.org/doi/10.1145/1273444.1254781
Ahn MLee JPaek YPande SLi Z(2007)Optimistic coalescing for heterogeneous register architecturesProceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems10.1145/1254766.1254781(93-102)Online publication date: 13-Jun-2007
https://dl.acm.org/doi/10.1145/1254766.1254781
Lee YChen C(2019)An effective and efficient code generation algorithm for uniform loops on non-orthogonal DSP architectureJournal of Systems and Software10.1016/j.jss.2006.06.00280:3(410-428)Online publication date: 2-Jan-2019
https://dl.acm.org/doi/10.1016/j.jss.2006.06.002

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