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Article

Modified booth truncated multipliers

Authors:

Alok A. Katkar,

James E. StineAuthors Info & Claims

GLSVLSI '04: Proceedings of the 14th ACM Great Lakes symposium on VLSI

Pages 444 - 447

https://doi.org/10.1145/988952.989059

Published: 26 April 2004 Publication History

Abstract

Truncated multiplication provides an efficient method for reducing the power dissipation and area of rounded parallel multipliers in digital signal processing systems. With this technique, the products of parallel multipliers are rounded to a shorter word size and the least-significant columns of the multiplication matrix are not used. This technique provides significant savings in terms of power dissipation for unsigned multiplication. Although previous implementations involved unsigned and signed array and tree multipliers, this technique can be equally applied to multiplication using Booth-encoding. This paper presents the design and implementation of parallel and truncated multipliers that use Booth-encoding and compressors for signed multiplication. Initial estimates indicate that truncated parallel multipliers dissipate less power than standard parallel multipliers for operand sizes of 16 bits.

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Cited By

Syed NMeher PVinod A(2018)Efficient Cross-Correlation Algorithm and Architecture for Robust Synchronization in Frame-Based Communication SystemsCircuits, Systems, and Signal Processing10.1007/s00034-017-0678-337:6(2548-2573)Online publication date: 1-Jun-2018
https://dl.acm.org/doi/10.1007/s00034-017-0678-3
Chen Y(2015)Area-Efficient Fixed-Width Squarer With Dynamic Error-Compensation CircuitIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2015.243575262:9(851-855)Online publication date: Sep-2015
https://doi.org/10.1109/TCSII.2015.2435752
Drane TRose TConstantinides G(2014)On the Systematic Creation of Faithfully Rounded Truncated Multipliers and ArraysIEEE Transactions on Computers10.1109/TC.2013.12663:10(2513-2525)Online publication date: 1-Oct-2014
https://dl.acm.org/doi/10.1109/TC.2013.126
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Index Terms

Modified booth truncated multipliers
1. Hardware

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Published In

cover image ACM Conferences

GLSVLSI '04: Proceedings of the 14th ACM Great Lakes symposium on VLSI

April 2004

479 pages

ISBN:1581138539

DOI:10.1145/988952

General Chair:
David Garrett
Bell Labs Research, Lucent Technologies
,
Program Chairs:
John Lach
University of Virginia
,
Charles Zukowski
Columbia University

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 26 April 2004

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April 26 - 28, 2004

MA, Boston, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Syed NMeher PVinod A(2018)Efficient Cross-Correlation Algorithm and Architecture for Robust Synchronization in Frame-Based Communication SystemsCircuits, Systems, and Signal Processing10.1007/s00034-017-0678-337:6(2548-2573)Online publication date: 1-Jun-2018
https://dl.acm.org/doi/10.1007/s00034-017-0678-3
Chen Y(2015)Area-Efficient Fixed-Width Squarer With Dynamic Error-Compensation CircuitIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2015.243575262:9(851-855)Online publication date: Sep-2015
https://doi.org/10.1109/TCSII.2015.2435752
Drane TRose TConstantinides G(2014)On the Systematic Creation of Faithfully Rounded Truncated Multipliers and ArraysIEEE Transactions on Computers10.1109/TC.2013.12663:10(2513-2525)Online publication date: 1-Oct-2014
https://dl.acm.org/doi/10.1109/TC.2013.126
Erez SEven G(2008)An improved micro-architecture for function approximation using piecewise quadratic interpolation2008 IEEE International Conference on Computer Design10.1109/ICCD.2008.4751895(422-426)Online publication date: Oct-2008
https://doi.org/10.1109/ICCD.2008.4751895
Maidee PHakim NBazargan K(2008)FPGA family composition and effects of specialized blocks2008 International Conference on Field Programmable Logic and Applications10.1109/FPL.2008.4629915(101-106)Online publication date: Sep-2008
https://doi.org/10.1109/FPL.2008.4629915

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