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Modular requirements for digital logic simulation at a predefined functional level

Authors:

S. A. SzygendaAuthors Info & Claims

ACM '72: Proceedings of the ACM annual conference - Volume 1

Pages 380 - 389

https://doi.org/10.1145/800193.569948

Published: 01 August 1972 Publication History

Abstract

Simulation of digital logic provides a viable technique for development and diagnosis of digital systems. Simulation models currently employed are discussed with a summary of structure and timing techniques. A methodology for functional simulation in conjunction with gate level simulation is discussed, presenting a representative set of predefined functions, and introducing a measure for predefined function performance. Errors in design detectable at the functional level are catagorized.

References

[1]

Armstrong, D. B. "On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic Nets." IEEE Trans. on Elec. Computers, vol, EC-15, no. 1, Feb. 1966, pp. 66-73

[2]

Breuer, M. A. "Functional Partitioning and Simulation of Digital Circuits. IEEE Trans. on Computers, vol. C-19, Nov., 1970, pp. 1038-46.

[3]

Chang, H. Y., Manning, E. G., and Metze, G. Fault Diagnosis of Digital Systems.1970, John Wiley & Sons, New York.

[4]

Chang, H. Y., and Manning, E. G. "Functional Techniques for Efficient Digital Fault Simulation." Digest of the First IEEE Computer Group Conference, 1967.

[5]

Chu, Y. Digital Computer Design Fundamentals. 1962, McGraw-Hill, New York.

[6]

Cohen, D. J. Computer Based Fault Analysis of Digital Systems. Research Report CSRR2020, University of Waterloo, Dept. of Applied Analysis and Computer Science, Waterloo, Canada, 1970.

[7]

Gschwind, H. W. Design on Digital Computers. 1967, Springer Verlag, New York.

[8]

Hardie, F. H., and Suhockie, R. J. "Design and Use of Fault Simulation for Saturn Computer Design." IEEE Trans. on Elec. Computers, vol. EC-16, August 1967, pp. 412-29.

[9]

Hays, G. G. "Computer-Aided Design: Simulation of Digital Design Logic." IEEE Trans. on Computers, vol. C-18, no. 1, January 1969, pp. 1-10.

[10]

Husson, S. S. "Microprogramming Manual for the IBM System 360 Model 50," IBM TR 00.1479-1, IBM Systems Development Division, Poughkeepsie, New York, 1967

[11]

Jephson, J. S.; McQuarrie, R. P.; and Vogelsberg, R. E. "A Three-Value Computer Design Verification System." IBM System Journal, no. 3, 1969, pp. 178-80.

Digital Library

[12]

McCluskey, E. J. Introduction to the Theory of Switching Circuits. 1965 McGraw-Hill, New York

[13]

McKay, A. R. "Comment on Computer-Aided Design: Simulation of Digital Design Logic." IEEE Trans. on Computers, September 1969, p. 862.

[14]

Miller, R. E. Switching Theory. 2 vols. 1965, John Wiley & Sons, New York.

[15]

Poage, J. F. "Derivation of Optimal Tests to Detect Faults in Combinational Logic." Symposium on Mathematical Automata, pp. 483-528), 1962 Brooklyn Polytechnic Press, Brooklyn

[16]

Roth, J. P. "Diagnosis of Automata Failures: A Calculus and a Method." IBM Journal, July 1966, pp. 278-291.

Digital Library

[17]

Seshu, S. "On an Improved Diagnosis Program." IEEE Trans. on Elec. Computers, vol. EC-14, February 1965, pp. 76-9.

[18]

Seshu, S., and Freeman, D. N. "The Diagnosis of Asynchronous Sequential Switching Systems." IEEE Trans. on Elec. Computers, August 1962, pp. 459-65.

[19]

Szygenda, S. A.; Rouse, D.; and Thompson, E. "A Model and Implementation of a Universal Time Delay Simulator for Large Digital Nets." AFIPS Proceedings of the SJCC, May 1970, pp. 207-16.

[20]

Szygenda, S. A., "TEGAS2 - Anatomy of a General Purpose Test Generation and Simulation System for Digital Logic." Proceedings of the 9th Annual Design Automation Workshop, June, 1972, Dallas, Texas.

Digital Library

[21]

Unger, S. H. Asynchronous Sequential Switching Circuits. 1969 John Wiley and Sons, New York.

Digital Library

[22]

Ulrich, E. G. "Exclusive Simulation of Activity in Digital Networks." Communications of the ACM, vol. 12, no. 6, February 1969, pp. 102-110.

Digital Library

[23]

Ulrich, E. G. "Time-Sequential Logical Simulation based on Circuit Delay and Selective Tracing of Active Network Paths.: Proceedings of the 20th ACM National Conference, August 1965.

Digital Library

[24]

Walford, R. B. "The Lamp System. "Proceedings of Workshop on Fault Detection and Diagnosis in Digital Circuits and Systems, Lehigh Univ., December, 1970.

[25]

Yetter, I. H. "High Speed Fault Simulation for Univac 1107 Computer System." Proceedings of the 23rd ACM National Conference, 1968, pp. 265-277.

Digital Library

[26]

Szygenda, S. A. and Goldbogen, G. C. "Implementation and Extension of Multi-Dimensional Path Sensitizing in a Simulation and Diagnostic System," Proceedings Seventh Annual Allerton Conference on Circuit and System Theory, University of Illinois, Monticello Illinois, October 1969.

[27]

Hemming, C. W. "Functional Simulation Techniques for design verification and fault insertion in electronic digital systems." Ph.D. Dissertation, CS/OR Center, Institute of Technology, Southern Methodist University, Dallas, Texas, September 1971.

[28]

Szygenda, S. A., Hemming, C. W., and Hemphill, J. M. "Time Flow Mechanisms for Use in Digital Logic Simulation," Proceedings of the Fifth Annual Conference on Applications of Simulation," (ACM) New York, N. Y., December, 1971.

Digital Library

[29]

Szygenda, S. A., et al., "Implementation of Synthesized Techniques for a Comprehensive Digital Design, Verification and Diagnosis System," Fifth International Conference on System Sciences, University of Hawaii, January, 1972.

Cited By

Miller DThornton M(2007)Multiple Valued Logic: Concepts and RepresentationsSynthesis Lectures on Digital Circuits and Systems10.2200/S00065ED1V01Y200709DCS0122:1(1-127)Online publication date: Jan-2007
https://doi.org/10.2200/S00065ED1V01Y200709DCS012
Gunes MThornton MKocan FSzygenda S(2005)A survey and comparison of digital logic simulators48th Midwest Symposium on Circuits and Systems, 2005.10.1109/MWSCAS.2005.1594208(744-749 Vol. 1)Online publication date: 2005
https://doi.org/10.1109/MWSCAS.2005.1594208
Bray D(1975)Multilevel functional simulationSIMULATION10.1177/00375497750250040625:4(121-126)Online publication date: 1-Oct-1975
https://doi.org/10.1177/003754977502500406
Show More Cited By

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Published In

cover image ACM Conferences

ACM '72: Proceedings of the ACM annual conference - Volume 1

August 1972

194 pages

ISBN:9781450374910

DOI:10.1145/800193

Copyright © 1972 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 August 1972

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August 1, 1972

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Cited By

Miller DThornton M(2007)Multiple Valued Logic: Concepts and RepresentationsSynthesis Lectures on Digital Circuits and Systems10.2200/S00065ED1V01Y200709DCS0122:1(1-127)Online publication date: Jan-2007
https://doi.org/10.2200/S00065ED1V01Y200709DCS012
Gunes MThornton MKocan FSzygenda S(2005)A survey and comparison of digital logic simulators48th Midwest Symposium on Circuits and Systems, 2005.10.1109/MWSCAS.2005.1594208(744-749 Vol. 1)Online publication date: 2005
https://doi.org/10.1109/MWSCAS.2005.1594208
Bray D(1975)Multilevel functional simulationSIMULATION10.1177/00375497750250040625:4(121-126)Online publication date: 1-Oct-1975
https://doi.org/10.1177/003754977502500406
Szygenda SLekkos AGaley JWall HHitchcock RBritt BMerwin RHumcke DSmithhisler D(1973)Integrated techniques for functional and gate-level digital logic simulationProceedings of the 10th Design Automation Workshop10.5555/800124.804011(159-172)Online publication date: 25-Jun-1973
https://dl.acm.org/doi/10.5555/800124.804011

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