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CMOS stuck-open fault detection using single test patterns

Authors:

R. Rajsuman,

A. P. Jayasumana,

Y. K. MalaiyaAuthors Info & Claims

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

Pages 714 - 717

https://doi.org/10.1145/74382.74511

Published: 01 June 1989 Publication History

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Abstract

CMOS combinational circuits exhibit sequential behavior in the presence of open faults, thus making it necessary to use two pattern tests. Two or multi-pattern sequences may fail to detect CMOS stuck-open faults in the presence of glitches. The available methods for augmenting CMOS gates to test CMOS stuck-open faults, are found to be inadequate in the presence of glitches. A new CMOS testable design is presented. The scheme uses two additional MOSFETs, which convert a CMOS gate to either pseudo nMos or pseudo pMOS gate during testing. The proposed design ensures the detection of stuck-open faults using a single vector during testing

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R. Rajsuman, A. P. Jayasumana and Y. K. M alaiya, "CMOS open fault detection in presence of glitches and timing skews", Submitted to IEEE J. Solid State Circuits.

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Cited By

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Sachdev MGyvez J(2007)Digital CMOS Fault ModelingDefect-Oriented Testing for Nano-Metric CMOS VLSI Circuits10.1007/0-387-46547-2_3(69-110)Online publication date: 2007
https://doi.org/10.1007/0-387-46547-2_3
Rullán MOliver JFerrer CBlom F(2007)Testability enhancement of a basic set of CMOS cellsQuality and Reliability Engineering International10.1002/qre.468010040610:4(279-288)Online publication date: 3-Jan-2007
https://doi.org/10.1002/qre.4680100406
Rülling W(2003)Design for TestabilityThe Electronic Design Automation Handbook10.1007/978-0-387-73543-6_15(339-381)Online publication date: 2003
https://doi.org/10.1007/978-0-387-73543-6_15
Show More Cited By

Index Terms

CMOS stuck-open fault detection using single test patterns
1. Hardware
  1. Hardware test
    1. Design for testability
  2. Integrated circuits
    1. Logic circuits
      1. Combinational circuits

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Information

Published In

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

June 1989

839 pages

ISBN:0897913108

DOI:10.1145/74382

Chairman:
Donald E. Thomas
Carnegie Mellon Univ., Pittsburgh, PA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1989

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DAC89

Sponsor:

IEEE-CS\TCDA
SIGDA

DAC89: The 26th ACM/IEEE-CS Design Automation Conference

June 25 - 28, 1989

Nevada, Las Vegas, USA

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DAC '89 Paper Acceptance Rate 156 of 465 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Sachdev MGyvez J(2007)Digital CMOS Fault ModelingDefect-Oriented Testing for Nano-Metric CMOS VLSI Circuits10.1007/0-387-46547-2_3(69-110)Online publication date: 2007
https://doi.org/10.1007/0-387-46547-2_3
Rullán MOliver JFerrer CBlom F(2007)Testability enhancement of a basic set of CMOS cellsQuality and Reliability Engineering International10.1002/qre.468010040610:4(279-288)Online publication date: 3-Jan-2007
https://doi.org/10.1002/qre.4680100406
Rülling W(2003)Design for TestabilityThe Electronic Design Automation Handbook10.1007/978-0-387-73543-6_15(339-381)Online publication date: 2003
https://doi.org/10.1007/978-0-387-73543-6_15
Sachdev MSachdev M(1999)Digital CMOS Fault Modeling and Inductive Fault AnalysisDefect Oriented Testing for CMOS Analog and Digital Circuits10.1007/978-1-4757-4926-7_2(15-63)Online publication date: 1999
https://doi.org/10.1007/978-1-4757-4926-7_2
Rullan MBlom FOliver JFerrer C(1993)Layout-level design for testability rules for a CMOS cell libraryProceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference10.1109/EURDAC.1993.410640(214-218)Online publication date: 1993
https://doi.org/10.1109/EURDAC.1993.410640
Blom FOliver JRullan MFerrer C(1993)Layout level design for testability strategy applied to a CMOS cell libraryProceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems10.1109/DFTVS.1993.595782(199-206)Online publication date: 1993
https://doi.org/10.1109/DFTVS.1993.595782
Jayasumana AMalaiya YRajsuman R(1991)Design of CMOS circuits for stuck-open fault testabilityIEEE Journal of Solid-State Circuits10.1109/4.6571126:1(58-61)Online publication date: Jan-1991
https://doi.org/10.1109/4.65711
Lee KBreuer M(1990)On the charge sharing problem in CMOS stuck-open fault testingProceedings. International Test Conference 199010.1109/TEST.1990.114050(417-426)Online publication date: 1990
https://doi.org/10.1109/TEST.1990.114050
Rajsuman RGupta B(1989)THCMOS: testable high speed CMOS designTwenty-Third Asilomar Conference on Signals, Systems and Computers, 1989.10.1109/ACSSC.1989.1200825(420-425)Online publication date: 1989
https://doi.org/10.1109/ACSSC.1989.1200825
Rajsuman RJayasumana AMalaiya Y(1989)CMOS open-fault detection in the presence of glitches and timing skewsIEEE Journal of Solid-State Circuits10.1109/4.3409224:4(1055-1061)Online publication date: Jan-1989
https://doi.org/10.1109/4.34092

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