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Quick piping: a fast, high-level model for describing processor pipelines

Published: 19 June 2002 Publication History

Abstract

Responding to marketplace needs, today's embedded processors must feature a flexible core that allows easy modification with fast time to market. In this environment, embedded processors are increasingly reliant on flexible support tools. This paper presents one such tool, called Quick Piping, a new, high-level formalism for modeling processor pipelines. Quick Piping consists of three primary components that together provide an easy-to-build, reusable processor description:
Pipeline graphs-a new high-level formalism for modeling processor pipelines,
pipe--a companion domain-specific language for specifying a pipeline graph,
pipe miner--a compiler specification generator for pipe descriptions. pipe miner processes a pipe description and produces a compiler specification that is used to build a compiler that reads the corresponding machine's instruction set and automatically generates resource vectors
.Despite their ubiquity and importance in achieving high performance in modern processors, pipelines--and improving the mechanisms for specifying their operation--have received little attention. Until now, handwritten resource vectors have served to specify information about a processor's pipeline and encode relevant information about each instruction's resource usage. Describing the complete set of resource vectors for a machine can be quite tedious and error prone, since it commonly must be developed by hand on an instruction-by-instruction basis.With its use of pipeline graphs, the pipe language, and the pipe miner compiler specification generator, Quick Piping gives the embedded processor architect and compiler writer an intuitive high-level abstraction of pipelines, a language for specifying a pipeline, and a tool for automatically producing pipeline resource vectors. The resulting specifications are quick to develop, easy to understand, simple to modify and maintain, and can be automatically processed to produce the low-level information required by processor control units and instruction schedulers.

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Published In

cover image ACM SIGPLAN Notices
ACM SIGPLAN Notices  Volume 37, Issue 7
July 2002
232 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/566225
Issue’s Table of Contents
  • cover image ACM Conferences
    LCTES/SCOPES '02: Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
    June 2002
    244 pages
    ISBN:1581135270
    DOI:10.1145/513829
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 June 2002
Published in SIGPLAN Volume 37, Issue 7

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Author Tags

  1. embedded systems
  2. modeling of computer architecture
  3. pipelines

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