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Efficient instruction scheduling using finite state automata

Authors:

Vasanth Bala,

Norman RubinAuthors Info & Claims

International Journal of Parallel Programming, Volume 25, Issue 2

Pages 53 - 82

https://doi.org/10.1007/BF02700047

Published: 01 April 1997 Publication History

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Jääskeläinen PGuzma VTakala J(2007)Resource conflict detection in simulation of function unit pipelinesProceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation10.5555/1776200.1776233(233-240)Online publication date: 16-Jul-2007
https://dl.acm.org/doi/10.5555/1776200.1776233
Grun PHalambi ADutt NNicolau A(2003)RTGENIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81301111:4(731-737)Online publication date: 1-Aug-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.813011
Milner CDavidson J(2002)Quick pipingACM SIGPLAN Notices10.1145/566225.51385937:7(175-184)Online publication date: 19-Jun-2002
https://dl.acm.org/doi/10.1145/566225.513859
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Efficient instruction scheduling using finite state automata

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Information

Published In

cover image International Journal of Parallel Programming

International Journal of Parallel Programming Volume 25, Issue 2

Special issue on instruction-level parallel processing—part I

April 1997

94 pages

ISSN:0885-7458

Editors:
Kemal Ebcioglu
IBM T J Watson Research Center, Hawthorne, NY
,
Wen-mei Hwu
Univ. of Illinois, Urbana-Champaign
,
Utpal Banerjee
Intel Corp., Santa Clara, CA
,
David Gelernter
Yale Univ., New Haven, CT
,
Alex Nicolau
Yale Univ., New Haven, CT
,
David Padua
Univ. of Illinois at Urbana-Champaign, Urbana, IL

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Kluwer Academic Publishers

United States

Publication History

Published: 01 April 1997

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Jääskeläinen PGuzma VTakala J(2007)Resource conflict detection in simulation of function unit pipelinesProceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation10.5555/1776200.1776233(233-240)Online publication date: 16-Jul-2007
https://dl.acm.org/doi/10.5555/1776200.1776233
Grun PHalambi ADutt NNicolau A(2003)RTGENIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81301111:4(731-737)Online publication date: 1-Aug-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.813011
Milner CDavidson J(2002)Quick pipingACM SIGPLAN Notices10.1145/566225.51385937:7(175-184)Online publication date: 19-Jun-2002
https://dl.acm.org/doi/10.1145/566225.513859
Milner CDavidson JMarwedel PDevadas S(2002)Quick pipingProceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems10.1145/513829.513859(175-184)Online publication date: 19-Jun-2002
https://dl.acm.org/doi/10.1145/513829.513859
Baev IMeleis WAbraham S(2002)Backtracking-Based Instruction Scheduling to Fill Branch Delay SlotsInternational Journal of Parallel Programming10.1023/A:102060111039130:6(397-418)Online publication date: 1-Dec-2002
https://dl.acm.org/doi/10.1023/A%3A1020601110391
Grun PHalambi ADutt NNicolau A(1999)RTGENProceedings of the 12th international symposium on System synthesis10.5555/857198.857961Online publication date: 1-Nov-1999
https://dl.acm.org/doi/10.5555/857198.857961
Gyllenhaal JHwu WRau B(1998)Optimization of Machine Descriptions for Efficient UseInternational Journal of Parallel Programming10.5555/608714.60875326:4(417-447)Online publication date: 1-Aug-1998
https://dl.acm.org/doi/10.5555/608714.608753

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Recommendations

Instruction scheduling for the HP PA-8000

Run-time versus compile-time instruction scheduling in superscalar (RISC) processors: performance and tradeoffs

Backtracking-Based Instruction Scheduling to Fill Branch Delay Slots

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