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Article

Implementing asynchronous circuits using a conventional EDA tool-flow

Author:

Christos P. SotiriouAuthors Info & Claims

DAC '02: Proceedings of the 39th annual Design Automation Conference

Pages 415 - 418

https://doi.org/10.1145/513918.514025

Published: 10 June 2002 Publication History

Abstract

This paper presents an approach by which asynchronous circuits can be realised with a conventional EDA tool flow and conventional standard cell libraries. Based on a gate-level asynchronous circuit implementation technique, direct-mapping, and by identifying the delay constraints and exploiting certain EDA tool features, this paper demonstrates that a conventional EDA tool flow can be used to describe, place, route and timing-verify asynchronous circuits.

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Cited By

Yang YHe JManohar RXie Y(2020)DaliProceedings of the 39th International Conference on Computer-Aided Design10.1145/3400302.3415689(1-9)Online publication date: 2-Nov-2020
https://dl.acm.org/doi/10.1145/3400302.3415689
IIZUKA MHAMADA NSAITO H(2013)An ASIC Design Support Tool Set for Non-pipelined Asynchronous Circuits with Bundled-Data ImplementationIEICE Transactions on Electronics10.1587/transele.E96.C.482E96.C:4(482-491)Online publication date: 2013
https://doi.org/10.1587/transele.E96.C.482
Nagy LStopjakova VZalusky R(2013)Completion detection in dual-rail asynchronous systems by current-sensingMicroelectronics Journal10.1016/j.mejo.2013.03.01444:6(538-544)Online publication date: Jun-2013
https://doi.org/10.1016/j.mejo.2013.03.014
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Index Terms

Implementing asynchronous circuits using a conventional EDA tool-flow
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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Published In

cover image ACM Conferences

DAC '02: Proceedings of the 39th annual Design Automation Conference

June 2002

956 pages

ISBN:1581134614

DOI:10.1145/513918

General Chair:
Bryan Ackland
Agere Systems, Inc., Holmdel, NJ

Copyright © 2002 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 June 2002

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DAC02: 39th Design Automation Conference

June 10 - 14, 2002

Louisiana, New Orleans, USA

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DAC '02 Paper Acceptance Rate 147 of 491 submissions, 30%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Citations

Cited By

Yang YHe JManohar RXie Y(2020)DaliProceedings of the 39th International Conference on Computer-Aided Design10.1145/3400302.3415689(1-9)Online publication date: 2-Nov-2020
https://dl.acm.org/doi/10.1145/3400302.3415689
IIZUKA MHAMADA NSAITO H(2013)An ASIC Design Support Tool Set for Non-pipelined Asynchronous Circuits with Bundled-Data ImplementationIEICE Transactions on Electronics10.1587/transele.E96.C.482E96.C:4(482-491)Online publication date: 2013
https://doi.org/10.1587/transele.E96.C.482
Nagy LStopjakova VZalusky R(2013)Completion detection in dual-rail asynchronous systems by current-sensingMicroelectronics Journal10.1016/j.mejo.2013.03.01444:6(538-544)Online publication date: Jun-2013
https://doi.org/10.1016/j.mejo.2013.03.014
Plana LClark DDavidson SFurber SGarside JPainkras EPepper JTemple SBainbridge J(2011)SpiNNakerACM Journal on Emerging Technologies in Computing Systems10.1145/2043643.20436477:4(1-18)Online publication date: 1-Dec-2011
https://dl.acm.org/doi/10.1145/2043643.2043647
Iizuka MHamada NSaito HYamaguchi RYoshinaga M(2011)A tool set for the design of asynchronous circuits with bundled-data implementationProceedings of the 2011 IEEE 29th International Conference on Computer Design10.1109/ICCD.2011.6081379(78-83)Online publication date: 9-Oct-2011
https://dl.acm.org/doi/10.1109/ICCD.2011.6081379
SAITO H(2009)Techniques for Asynchronous Circuit Design非同期式回路の設計技術IEICE ESS Fundamentals Review10.1587/essfr.3.3_643:3(64-70)Online publication date: 2009
https://doi.org/10.1587/essfr.3.3_64
Tranchero MReyneri L(2009)Exploiting synchronous placement for asynchronous circuits onto commercial FPGAs2009 International Conference on Field Programmable Logic and Applications10.1109/FPL.2009.5272378(622-625)Online publication date: Aug-2009
https://doi.org/10.1109/FPL.2009.5272378
Oreifej RAlsharqawi AEjnioui A(2006)Synthesis of Pipelined SRSL CircuitsProceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures10.1109/ISVLSI.2006.86Online publication date: 2-Mar-2006
https://dl.acm.org/doi/10.1109/ISVLSI.2006.86
Oreifej RAlsharqawi AEjnioui A(2005)Pipeline synthesis of SRSL circuits2005 12th IEEE International Conference on Electronics, Circuits and Systems10.1109/ICECS.2005.4633512(1-4)Online publication date: Dec-2005
https://doi.org/10.1109/ICECS.2005.4633512
Papaefstathiou IPapaefstathiou VSotiriou C(2004)Design-space exploration of the most widely used cryptography algorithmsMicroprocessors and Microsystems10.1016/j.micpro.2004.08.00928:10(561-571)Online publication date: Dec-2004
https://doi.org/10.1016/j.micpro.2004.08.009
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