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Article

The tangram framework (embedded tutorial): asynchronous circuits for low power

Authors:

Ad PeetersAuthors Info & Claims

ASP-DAC '01: Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Pages 255 - 260

https://doi.org/10.1145/370155.370339

Published: 30 January 2001 Publication History

Abstract

Asynchronous CMOS circuits have the potential for very low power consumption, because they only dissipate when and where active. In addition they have favorable EMC properties, since they emit less energy, which in addition is evenly distributed over the spectrum. The Tangram framework supports the design of asynchronous circuits in a high-level programming language. Using this framework we have designed several chips, such as for instance for pagers and smart cards, which are clearly superior to synchronous designs.

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Cited By

Bouzafour ARenaudin MGaravel HMateescu RSerwe W(2018)Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)10.1109/ASYNC.2018.00021(34-42)Online publication date: May-2018
https://doi.org/10.1109/ASYNC.2018.00021
Bhadra DStevens K(2017)Design of a low power, relative timing based asynchronous MSP430 microprocessorProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130571(794-799)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130571
Liu NChong KHo WGwee BChang JFanucci LTeich J(2016)Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applicationsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972004(850-853)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972004
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The tangram framework (embedded tutorial): asynchronous circuits for low power

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cover image ACM Conferences

ASP-DAC '01: Proceedings of the 2001 Asia and South Pacific Design Automation Conference

January 2001

662 pages

ISBN:0780366344

DOI:10.1145/370155

Chairman:
Satoshi Goto
NEC Corp., Kawasaki, Japan

Copyright © 2001 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 30 January 2001

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

Bouzafour ARenaudin MGaravel HMateescu RSerwe W(2018)Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)10.1109/ASYNC.2018.00021(34-42)Online publication date: May-2018
https://doi.org/10.1109/ASYNC.2018.00021
Bhadra DStevens K(2017)Design of a low power, relative timing based asynchronous MSP430 microprocessorProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130571(794-799)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130571
Liu NChong KHo WGwee BChang JFanucci LTeich J(2016)Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applicationsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972004(850-853)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972004
Salaun GSerwe WThonnart YVivet P(2007)Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-ChipProceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems10.1109/ASYNC.2007.18(73-82)Online publication date: 12-Mar-2007
https://dl.acm.org/doi/10.1109/ASYNC.2007.18
Salaün GSerwe W(2005)Translating hardware process algebras into standard process algebrasProceedings of the 5th international conference on Integrated Formal Methods10.1007/11589976_17(287-306)Online publication date: 29-Nov-2005
https://dl.acm.org/doi/10.1007/11589976_17
Branover AKol RGinosar R(2004)Asynchronous Design By ConversionProceedings of the conference on Design, automation and test in Europe - Volume 210.5555/968879.969197Online publication date: 16-Feb-2004
https://dl.acm.org/doi/10.5555/968879.969197
Sacker MBrown ARushton AWilson P(2004)A behavioral synthesis system for asynchronous circuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2004.83294412:9(978-994)Online publication date: 1-Sep-2004
https://dl.acm.org/doi/10.1109/TVLSI.2004.832944
Sacker MBrown AWilson PRushton A(2004)A general purpose behavioural asynchronous synthesis system10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings.10.1109/ASYNC.2004.1299294(125-134)Online publication date: 2004
https://doi.org/10.1109/ASYNC.2004.1299294
Peeters A(2004)Implementation of handshake componentsProceedings of the 2004 international conference on Communicating Sequential Processes: the First 25 Years10.1007/11423348_7(98-132)Online publication date: 7-Jul-2004
https://dl.acm.org/doi/10.1007/11423348_7
Amde MBlunno ISotiriou CGetreu IFix LLavagno L(2003)Automating the design of an asynchronous DLX microprocessorProceedings of the 40th annual Design Automation Conference10.1145/775832.775961(502-507)Online publication date: 2-Jun-2003
https://dl.acm.org/doi/10.1145/775832.775961
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