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Congestion and Timing Aware Macro Placement Using Machine Learning Predictions from Different Data Sources: Cross-design Model Applicability and the Discerning Ensemble

Authors:

Pedja Raspopovic,

Menno E. Verbeek,

Vineet Rashingkar,

Amit JalotaAuthors Info & Claims

ISPD '22: Proceedings of the 2022 International Symposium on Physical Design

Pages 195 - 202

https://doi.org/10.1145/3505170.3506722

Published: 13 April 2022 Publication History

Abstract

Modern very large-scale integration (VLSI) designs typically use a lot of macros (RAM, ROM, IP) that occupy a large portion of the core area. Also, macro placement being an early stage of the physical design flow, followed by standard cell placement, physical synthesis (place-opt), clock tree synthesis and routing, etc., has a big impact on the final quality of result (QoR). There is a need for Electronic Design Automation (EDA) physical design tools to provide predictions for congestion, timing, and power etc., with certainty for different macro placements before running time-consuming flows. However, the diversity of IC designs that commercial EDA tools must support and the limited number of similar designs that can provide training data, make such machine learning (ML) predictions extremely hard. Because of this, ML models usually need to be completely retrained for unseen designs to work properly. However, collecting full flow macro placement ML data is time consuming and impractical. To make things worse, common ML methods, such as regression, support vector machine (SVM), random forest (RF), neural network (NN) in general, lack a good estimation of prediction accuracy or confidence and lack debuggability for cross-design applications. In this paper, we present a novel discerning ensemble technique for cross-design ML prediction for macro placement. We developed our solution based on a large number of designs with different design styles and technology nodes, and tested the solution on 8 leading-edge industry designs and achieved comparable or even better results in a few hours (per design) than manual placement results that take many engineers weeks or even months to achieve. Our method shows great promise for many ML problems in EDA applications, or even in other areas.

References

[1]

I. L. Markov, J. Hu, and M. Kim, "Progress and Challenges in VLSI Placement Research", Proc. of the IEEE, 103(11) (2015), pp. 1985--2003

[2]

A. B. Kahng. 2018. Machine Learning Applications in Physical Design: Recent Results and Directions. In ISPD'18: 2018 International Symposium on Physical Design, March 25--28, 2018, Monterey, CA, USA. ACM, New York, NY, USA, 6 pages. https://doi.org/10.1145/3177540.3177554

[3]

A. B. Kahng, UCSD Depts. of CSE and ECE, La Jolla, CA 92093-0404 USA, [email protected] https://vlsicad.ucsd.edu/?abk/. 2021. Advancing Placement. In Proceedings of the 2021 International Symposium on Physical Design (ISPD '21), March 22--24, 2021, Virtual Event, USA. ACM, New York, NY, USA, 8 pages. https://doi.org/10.1145/3439706.3446884

[4]

G. Huang, J. Hu, Y. He, J. Liu, M. Ma, Z. Shen, J. Wu, Y. Xu, H. Zhang, K. Zhong, X. Ning, Y. Ma, H. Yang, B. Yu, H. Yang, and Y. Wang. 2021. Machine Learning for Electronic Design Automation: A Survey. 1, 1 (March 2021), 44 pages

[5]

Y. Lin, Z. Jiang, J. Gu, W. Li, S. Dhar, H. Ren, B. Khailany, and D. Z. Pan, "Dreamplace: Deep learning toolkit-enabled gpu acceleration for modern vlsi placement," IEEE TCAD, pp. 1--1, 2020.

[6]

K. Jeong and A. B. Kahng, "Methodology from Chaos in IC Implementation", Proc. ISQED, 2010, pp. 885--892.

[7]

A. B. Kahng and S. Mantik, "Measurement of Inherent Noise in EDA Tools", Proc. ISQED, 2002, pp. 206--211.

Digital Library

[8]

K. Jeong, A. B. Kahng, B. Lin, and K. Samadi. 2010. Accurate Machine-Learning-Based On-Chip Router Modeling. IEEE Embedded Systems Letters (ESL) 2, 3 (2010), 62--66.

Digital Library

[9]

W.-T. J. Chan, Y. D., A. B. Kahng, S. Nath, and K. Samadi. 2016. BEOL Stack-Aware Routability Prediction from Placement Using Data Mining Techniques. In IEEE International Conference on Computer Design (ICCD). 41--48.

[10]

W.-K. Cheng, Y.-Y. Guo, and C.-S. Wu, "Evaluation of Routability-driven Macro Placement with Machine-Learning Technique", The 7th IEEE International Symposium on Next-Generation Electronics (ISNE 2018)

[11]

Y. Huang, Z. Xie, G.-Q. Fang, T.-C. Yu, H. Ren, S.-Y. Fang, Y. Chen, and J. Hu, "Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model," 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, pp. 180--185.

[12]

A. Goldie and A. Mirhoseini. 2020. Placement Optimization with Deep Reinforcement Learning. In Proceedings of the 2020 International Symposium on Physical Design (ISPD '20), March 29-April 1, 2020, Taipei, Taiwan. ACM, New York, NY, USA, 5 pages. https://doi.org/10.1145/3372780.3378174

Digital Library

[13]

A. Mirhoseini, A. Goldie, M. Yazgan, J. Jiang, E. M. Songhori, S. Wang, Y.-J. Lee, E. Johnson, O. Pathak, S. Bae, A. Nazi, J. Pak, A. Tong, K. Srinivasa, W. Hang, E. Tuncer, A. Babu, Quoc V. Le, J. Laudon, R. C. Ho, R. Carpenter, and J. Dean. 2020. Chip Placement with Deep Reinforcement Learning. CoRR abs/2004.10746 (2020). arXiv:2004.10746

[14]

Z. Jiang, E. Songhori, S. Wang, A. Goldie, A. Mirhoseini, J. Jiang, Y.J. Lee, and D. Pan, 2021. Delving into Macro Placement with Reinforcement Learning. 1--3. 10.1109/MLCAD52597.2021.9531313.

[15]

S. I. Ward, D. Ding, and D. Z. Pan. 2012. PADE: A High-Performance Placer with Automatic Datapath Extraction and Evaluation Through High Dimensional Data Learning. In ACM/IEEE Design Automation Conference (DAC). 756--761.

[16]

S. I. Ward, M-C Kim, N. Viswanathan, Z. Li, C. J. Alpert, E. E. Swartzlander Jr., and D. Z. Pan. 2012. Keep it Straight: Teaching Placement How to Better Handle Designs with Datapaths. In ACM International Symposium on Physical Design (ISPD). 79--86.

[17]

D. Vashisht, H. Rampal, H. Liao, Y. Lu, D. Shanbhag, E. Fallon, and L.B. Kara. 2020. Placement in Integrated Circuits using Cyclic Reinforcement Learning and Simulated Annealing, arXiv:2011.07577v1 [cs.AI] 15 Nov 2020

[18]

Y.-C. Lu, S. Pentapati, and S. K. Lim. 2021. The Law of Attraction: Affinity-Aware Placement Optimization using Graph Neural Networks. In Proceedings of the 2021 International Symposium on Physical Design (ISPD '21), March 22--24, 2021, Virtual Event, USA. ACM, New York, NY, USA, 8 pages. https://doi.org/10.1145/3439706.3447045

Digital Library

[19]

W-T J. Chan, P-H Ho, A. B. Kahng, and P. Saxena. 2017. Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning. In Proceedings of the 2017 ACM on International Symposium on Physical Design (ISPD '17). Association for Computing Machinery, New York, NY, USA, 15--21. https://doi.org/10.1145/3036669.3036681

[20]

A. F. Tabrizi, N.K. Rakai, Darav, S. Xu, L. Rakai, I. Bustany, A. Kennings, and L. Behjat. "A Machine Learning Framework to Identify Detailed Routing Short Violations from a Placed Netlist." 2018 55th ACM/ESDA/IEEE Design Automation Conference (2018): 1--6.

[21]

P. Spindler and F. M. Johannes., 2007. Fast and Accurate Routing Demand Estimation for Efficient Routability-driven Placement. In Design, Automation & Test in Europe Conference & Exhibition (DATE).

Digital Library

[22]

Z. Xie, Y-H Huang, G-Q Fang, H. Ren, S-Y Fang, Y. Chen, and J. Hu. 2018. RouteNet: Routability Prediction for Mixed-Size Designs Using Convolutional Neural Network. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 80.

[23]

Z. Xie, H. Ren, B. Khailany, Y. Sheng, S. Santosh, J. Hu, and Y. Chen. 2020. PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network. In IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC). 13--18.

[24]

R. Liang, H. Xiang, D. Pandey, L. N. Reddy, S. Ramji, G-J Nam, and J. Hu. 2020. DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network. In ACM International Symposium on Physical Design (ISPD). 135--142.

[25]

R. Liang, Z. Xie, J. Jung, V. Chauha, Y. Chen, J. Hu, H. Xiang, and G. J. Nam. 2020. Routing-Free Crosstalk Prediction. In 2020 IEEE/ACM International Conference on Computer Aided Design (ICCAD). 1--9.

[26]

T-C Yu, S-Y Fang, H-S Chiu, K-S Hu, P. H-Y Tai, C. C-F Shen, and H. Sheng. 2020. Lookahead Placement Optimization with Cell Library-based Pin Accessibility Prediction via Active Learning. In Proceedings of the 2020 International Symposium on Physical Design (ISPD '20). Association for Computing Machinery, New York, NY, USA, 65--72. https://doi.org/10.1145/3372780.3375562

[27]

J. Chen, J. Kuang, G. Zhao, D. J. -H. Huang and E. F. Y. Young, "PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learning," 2020 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2020, pp. 1--8.

[28]

L. Li, Y. Cai and Q. Zhou, "An Efficient Approach for DRC Hotspot Prediction with Convolutional Neural Network," 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1--5.

[29]

D. H. Wolpert, (1992). Stacked generalization. Neural networks, 5(2), 241--259.

[30]

M. P. Perrone and L. N. Cooper, 1992. When networks disagree: Ensemble methods for hybrid neural networks: BROWN UNIV PROVIDENCE RI INST FOR BRAIN AND NEURAL SYSTEMS.

[31]

L. Breiman, (1996a). Bagging predictors. Machine learning, 24(2), 123--140.

[32]

Y. Freund, (1995). Boosting a weak learning algorithm by majority. Information and computation, 121(2), 256--285

[33]

T. Hastie, R. Tibshirani, and J. Friedman, 2009. "The Elements of Statistical learning: Data Mining, Inference and Prediction" 2nd Edition, Springer Science

[34]

T. Chen and C. Guestrin. 2016. XGboost: A scalable tree boosting system. In ACM International Conference on Knowledge Discovery and Data Mining (DMKD). 785--794.

[35]

W. Hamilton, Z. Ying, and J. Leskovec. 2017. Inductive representation learning on large graphs. In IEEE Conference and Workshop on Neural Information Processing Systems (NIPS). 1024--1034.

[36]

M. Shahhosseini, G. Hu, and H. Pham, "Optimizing Ensemble Weights and Hyperparameters of Machine Learning Models for Regression Problems"

Cited By

Lu YRen HHsiao HLim S(2024)GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer LearningACM Transactions on Design Automation of Electronic Systems10.1145/363646129:2(1-17)Online publication date: 14-Feb-2024
https://dl.acm.org/doi/10.1145/3636461
Lee PChen T(2024)AI-Driven Innovations in IC Designs: From Planning to Implementation2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)10.1109/VLSITSA60681.2024.10546365(1-2)Online publication date: 22-Apr-2024
https://doi.org/10.1109/VLSITSA60681.2024.10546365
Karimullah SVishnuvardhan DGunjan VShaik F(2024)Performance Evaluation of GA, HS, PSO Algorithms for Optimizing Area, Wirelength Using MCNC ArchitecturesModern Approaches in Machine Learning and Cognitive Science: A Walkthrough10.1007/978-3-031-43009-1_5(53-70)Online publication date: 14-Jan-2024
https://doi.org/10.1007/978-3-031-43009-1_5
Show More Cited By

Index Terms

Congestion and Timing Aware Macro Placement Using Machine Learning Predictions from Different Data Sources: Cross-design Model Applicability and the Discerning Ensemble
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement

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cover image ACM Conferences

ISPD '22: Proceedings of the 2022 International Symposium on Physical Design

April 2022

240 pages

ISBN:9781450392105

DOI:10.1145/3505170

General Chairs:
Laleh Behjat
University of Calgary, Canada
,
Stephen Yang
Leda Technology, USA

Copyright © 2022 ACM.

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Published: 13 April 2022

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March 27 - 30, 2022

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

Lu YRen HHsiao HLim S(2024)GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer LearningACM Transactions on Design Automation of Electronic Systems10.1145/363646129:2(1-17)Online publication date: 14-Feb-2024
https://dl.acm.org/doi/10.1145/3636461
Lee PChen T(2024)AI-Driven Innovations in IC Designs: From Planning to Implementation2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)10.1109/VLSITSA60681.2024.10546365(1-2)Online publication date: 22-Apr-2024
https://doi.org/10.1109/VLSITSA60681.2024.10546365
Karimullah SVishnuvardhan DGunjan VShaik F(2024)Performance Evaluation of GA, HS, PSO Algorithms for Optimizing Area, Wirelength Using MCNC ArchitecturesModern Approaches in Machine Learning and Cognitive Science: A Walkthrough10.1007/978-3-031-43009-1_5(53-70)Online publication date: 14-Jan-2024
https://doi.org/10.1007/978-3-031-43009-1_5
Liu B(2023)SRAM Compilation and Placement Co-Optimization for Memory SubsystemsElectronics10.3390/electronics1206135312:6(1353)Online publication date: 12-Mar-2023
https://doi.org/10.3390/electronics12061353
Qiu YXing YZheng XGao PCai SXiong X(2023)Progress of Placement Optimization for Accelerating VLSI Physical DesignElectronics10.3390/electronics1202033712:2(337)Online publication date: 9-Jan-2023
https://doi.org/10.3390/electronics12020337
Lu YRen HHsiao HLim SChinnery DHui-Ru Jiang I(2023)DREAM-GANProceedings of the 2023 International Symposium on Physical Design10.1145/3569052.3572993(141-148)Online publication date: 26-Mar-2023
https://dl.acm.org/doi/10.1145/3569052.3572993
Lu YYang TLim SRen HFranzon PKahng ALi HLi B(2022)Placement Optimization via PPA-Directed Graph ClusteringProceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD10.1145/3551901.3556482(1-6)Online publication date: 12-Sep-2022
https://dl.acm.org/doi/10.1145/3551901.3556482
Lu YYang TLim SRen H(2022)Placement Optimization via PPA-Directed Graph Clustering2022 ACM/IEEE 4th Workshop on Machine Learning for CAD (MLCAD)10.1109/MLCAD55463.2022.9900089(1-6)Online publication date: 12-Sep-2022
https://doi.org/10.1109/MLCAD55463.2022.9900089

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