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Analysis and minimization of test time in a combined BIST and external test approach

Authors:

Makoto Sugihara,

Hiroto YasuuraAuthors Info & Claims

DATE '00: Proceedings of the conference on Design, automation and test in Europe

Pages 134 - 140

https://doi.org/10.1145/343647.343719

Published: 01 January 2000 Publication History

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Cited By

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Karimi ETabandeh MHaghbayan M(2013)Test data compression strategy while using hybrid-BIST methodologyEast-West Design & Test Symposium (EWDTS 2013)10.1109/EWDTS.2013.6673168(1-5)Online publication date: Sep-2013
https://doi.org/10.1109/EWDTS.2013.6673168
Haghbayan MSafari SNavabi Z(2012)Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)10.1109/DDECS.2012.6219022(42-45)Online publication date: Apr-2012
https://doi.org/10.1109/DDECS.2012.6219022
Cota Éde Morais Amory ALubaszewski MCota Éde Morais Amory ASoares Lubaszewski M(2011)Systems-on-Chip TestingReliability, Availability and Serviceability of Networks-on-Chip10.1007/978-1-4614-0791-1_3(25-58)Online publication date: 14-Aug-2011
https://doi.org/10.1007/978-1-4614-0791-1_3
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Index Terms

Analysis and minimization of test time in a combined BIST and external test approach
1. Hardware

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Published In

DATE '00: Proceedings of the conference on Design, automation and test in Europe

January 2000

707 pages

ISBN:1581132441

DOI:10.1145/343647

Chairman:
Ivo Bolsens
IMEC, Leuven, Belgium

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 January 2000

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DATE00: Design Automation and Test in Europe

March 27 - 30, 2000

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all

Karimi ETabandeh MHaghbayan M(2013)Test data compression strategy while using hybrid-BIST methodologyEast-West Design & Test Symposium (EWDTS 2013)10.1109/EWDTS.2013.6673168(1-5)Online publication date: Sep-2013
https://doi.org/10.1109/EWDTS.2013.6673168
Haghbayan MSafari SNavabi Z(2012)Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)10.1109/DDECS.2012.6219022(42-45)Online publication date: Apr-2012
https://doi.org/10.1109/DDECS.2012.6219022
Cota Éde Morais Amory ALubaszewski MCota Éde Morais Amory ASoares Lubaszewski M(2011)Systems-on-Chip TestingReliability, Availability and Serviceability of Networks-on-Chip10.1007/978-1-4614-0791-1_3(25-58)Online publication date: 14-Aug-2011
https://doi.org/10.1007/978-1-4614-0791-1_3
Jervan GOrasson EKruus HUbar R(2008)Hybrid BIST optimization using reseeding and test set compactionMicroprocessors & Microsystems10.1016/j.micpro.2008.03.00732:5-6(254-262)Online publication date: 1-Aug-2008
https://dl.acm.org/doi/10.1016/j.micpro.2008.03.007
Jervan GKruus HOrasson EUbar R(2007)Optimization of Memory-Constrained Hybrid BIST for Testing Core-Based Systems2007 International Symposium on Industrial Embedded Systems10.1109/SIES.2007.4297319(71-77)Online publication date: Jul-2007
https://doi.org/10.1109/SIES.2007.4297319
Jervan GOrasson EKruus HUbar R(2007)Hybrid BIST Optimization Using Reseeding and Test Set Compaction10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)10.1109/DSD.2007.4341529(596-603)Online publication date: Aug-2007
https://doi.org/10.1109/DSD.2007.4341529
He ZPeng ZEles PGielen G(2006)Power constrained and defect-probability driven SoC test scheduling with test set partitioningProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131562(291-296)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131562
Larsson EPeng Z(2006)Power-Aware Test Planning in the Early System-on-Chip Design Exploration ProcessIEEE Transactions on Computers10.1109/TC.2006.2855:2(227-239)Online publication date: 1-Feb-2006
https://dl.acm.org/doi/10.1109/TC.2006.28
Jervan GShchenova TUbar R(2006)Hybrid BIST Scheduling for NoC-Based SoCs2006 NORCHIP10.1109/NORCHP.2006.329263(141-144)Online publication date: Nov-2006
https://doi.org/10.1109/NORCHP.2006.329263
Jervan GPeng ZShchenova TUbar R(2006)Hybrid BIST energy minimisation technique for system-on-chip testingIEE Proceedings - Computers and Digital Techniques10.1049/ip-cdt:20050064153:4(208)Online publication date: 2006
https://doi.org/10.1049/ip-cdt:20050064
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