Cited By
View all- Xu SXue HLuo LYan LZou XThapliyal HDeMara RPartin-Vaisband IKatkoori S(2023)DrPIM: An Adaptive and Less-blocking Data Replication Framework for Processing-in-Memory ArchitectureProceedings of the Great Lakes Symposium on VLSI 202310.1145/3583781.3590294(385-389)Online publication date: 5-Jun-2023
- Asri MGerstlauer A(2022)CASPHAr: Cache-Managed Accelerator Staging and Pipelining in Heterogeneous System ArchitecturesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319753541:11(4325-4336)Online publication date: Nov-2022
- Chen XWu YHan Y(2021)FePIMProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431530(114-119)Online publication date: 18-Jan-2021